stm32f10x_sdio.txt

STM32F103ZET6+UCOSII+UCGUI源码

;;;116    }
000018  4770              BX       lr
;;;117    
                          ENDP

00001a  0000              DCW      0x0000
                  |L10.28|
                          DCD      0x40018000
                  |L10.32|
                          DCD      0x00c007ff

                          AREA ||i.SDIO_GetCommandResponse||, CODE, READONLY, ALIGN=2

                  SDIO_GetCommandResponse PROC
;;;374    *******************************************************************************/
;;;375    u8 SDIO_GetCommandResponse(void)
000000  4801              LDR      r0,|L11.8|
;;;376    {
;;;377      return (u8)(SDIO->RESPCMD);
000002  6900              LDR      r0,[r0,#0x10]
000004  b2c0              UXTB     r0,r0
;;;378    }
000006  4770              BX       lr
;;;379    
                          ENDP

                  |L11.8|
                          DCD      0x40018000

                          AREA ||i.SDIO_GetDataCounter||, CODE, READONLY, ALIGN=2

                  SDIO_GetDataCounter PROC
;;;471    *******************************************************************************/
;;;472    u32 SDIO_GetDataCounter(void)
000000  4801              LDR      r0,|L12.8|
;;;473    { 
;;;474      return SDIO->DCOUNT;
000002  6b00              LDR      r0,[r0,#0x30]
;;;475    }
000004  4770              BX       lr
;;;476    
                          ENDP

000006  0000              DCW      0x0000
                  |L12.8|
                          DCD      0x40018000

                          AREA ||i.SDIO_GetFIFOCount||, CODE, READONLY, ALIGN=2

                  SDIO_GetFIFOCount PROC
;;;508    *******************************************************************************/
;;;509    u32 SDIO_GetFIFOCount(void)
000000  4801              LDR      r0,|L13.8|
;;;510    { 
;;;511      return SDIO->FIFOCNT;
000002  6c80              LDR      r0,[r0,#0x48]
;;;512    }
000004  4770              BX       lr
;;;513    
                          ENDP

000006  0000              DCW      0x0000
                  |L13.8|
                          DCD      0x40018000

                          AREA ||i.SDIO_GetFlagStatus||, CODE, READONLY, ALIGN=2

                  SDIO_GetFlagStatus PROC
;;;682    *******************************************************************************/
;;;683    FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG)
000000  4903              LDR      r1,|L14.16|
;;;684    { 
000002  4602              MOV      r2,r0
;;;685      FlagStatus bitstatus = RESET;
;;;686      
;;;687      /* Check the parameters */
;;;688      assert_param(IS_SDIO_FLAG(SDIO_FLAG));
;;;689      
;;;690      if ((SDIO->STA & SDIO_FLAG) != (u32)RESET)
000004  6b49              LDR      r1,[r1,#0x34]
000006  2000              MOVS     r0,#0                 ;685
000008  4211              TST      r1,r2
00000a  d000              BEQ      |L14.14|
;;;691      {
;;;692        bitstatus = SET;
00000c  2001              MOVS     r0,#1
                  |L14.14|
;;;693      }
;;;694      else
;;;695      {
;;;696        bitstatus = RESET;
;;;697      }
;;;698      return bitstatus;
;;;699    }
00000e  4770              BX       lr
;;;700    
                          ENDP

                  |L14.16|
                          DCD      0x40018000

                          AREA ||i.SDIO_GetITStatus||, CODE, READONLY, ALIGN=2

                  SDIO_GetITStatus PROC
;;;777    *******************************************************************************/
;;;778    ITStatus SDIO_GetITStatus(u32 SDIO_IT)
000000  4903              LDR      r1,|L15.16|
;;;779    { 
000002  4602              MOV      r2,r0
;;;780      ITStatus bitstatus = RESET;
;;;781      
;;;782      /* Check the parameters */
;;;783      assert_param(IS_SDIO_GET_IT(SDIO_IT));
;;;784    
;;;785      if ((SDIO->STA & SDIO_IT) != (u32)RESET)  
000004  6b49              LDR      r1,[r1,#0x34]
000006  2000              MOVS     r0,#0                 ;780
000008  4211              TST      r1,r2
00000a  d000              BEQ      |L15.14|
;;;786      {
;;;787        bitstatus = SET;
00000c  2001              MOVS     r0,#1
                  |L15.14|
;;;788      }
;;;789      else
;;;790      {
;;;791        bitstatus = RESET;
;;;792      }
;;;793      return bitstatus;
;;;794    }
00000e  4770              BX       lr
;;;795    
                          ENDP

                  |L15.16|
                          DCD      0x40018000

                          AREA ||i.SDIO_GetPowerState||, CODE, READONLY, ALIGN=2

                  SDIO_GetPowerState PROC
;;;224    *******************************************************************************/
;;;225    u32 SDIO_GetPowerState(void)
000000  4802              LDR      r0,|L16.12|
;;;226    {
;;;227      return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
000002  6800              LDR      r0,[r0,#0]
000004  f0000003          AND      r0,r0,#3
;;;228    }
000008  4770              BX       lr
;;;229    
                          ENDP

00000a  0000              DCW      0x0000
                  |L16.12|
                          DCD      0x40018000

                          AREA ||i.SDIO_GetResponse||, CODE, READONLY, ALIGN=2

                  SDIO_GetResponse PROC
;;;391    *******************************************************************************/
;;;392    u32 SDIO_GetResponse(u32 SDIO_RESP)
000000  4901              LDR      r1,|L17.8|
;;;393    {
;;;394      /* Check the parameters */
;;;395      assert_param(IS_SDIO_RESP(SDIO_RESP));
;;;396      
;;;397      return (*(vu32 *)(SDIO_RESP_ADDR + SDIO_RESP)); 
000002  4408              ADD      r0,r0,r1
000004  6940              LDR      r0,[r0,#0x14]
;;;398    }
000006  4770              BX       lr
;;;399    
                          ENDP

                  |L17.8|
                          DCD      0x40018000

                          AREA ||i.SDIO_ITConfig||, CODE, READONLY, ALIGN=2

                  SDIO_ITConfig PROC
;;;273    *******************************************************************************/
;;;274    void SDIO_ITConfig(u32 SDIO_IT, FunctionalState NewState)
000000  4a04              LDR      r2,|L18.20|
;;;275    {
;;;276      /* Check the parameters */
;;;277      assert_param(IS_SDIO_IT(SDIO_IT));
;;;278      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;279      
;;;280      if (NewState != DISABLE)
000002  2900              CMP      r1,#0
;;;281      {
;;;282        /* Enable the SDIO interrupts */
;;;283        SDIO->MASK |= SDIO_IT;
000004  6bd1              LDR      r1,[r2,#0x3c]
000006  d001              BEQ      |L18.12|
000008  4301              ORRS     r1,r1,r0
00000a  e000              B        |L18.14|
                  |L18.12|
;;;284      }
;;;285      else
;;;286      {
;;;287        /* Disable the SDIO interrupts */
;;;288        SDIO->MASK &= ~SDIO_IT;
00000c  4381              BICS     r1,r1,r0
                  |L18.14|
00000e  63d1              STR      r1,[r2,#0x3c]         ;283
;;;289      } 
;;;290    }
000010  4770              BX       lr
;;;291    
                          ENDP

000012  0000              DCW      0x0000
                  |L18.20|
                          DCD      0x40018000

                          AREA ||i.SDIO_Init||, CODE, READONLY, ALIGN=2

                  SDIO_Init PROC
;;;127    *******************************************************************************/
;;;128    void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
000000  b570              PUSH     {r4-r6,lr}
;;;129    {
;;;130      u32 tmpreg = 0;
;;;131        
;;;132      /* Check the parameters */
;;;133      assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
;;;134      assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
;;;135      assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
;;;136      assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
;;;137      assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); 
;;;138       
;;;139    /*---------------------------- SDIO CLKCR Configuration ------------------------*/  
;;;140      /* Get the SDIO CLKCR value */
;;;141      tmpreg = SDIO->CLKCR;
000002  4b09              LDR      r3,|L19.40|
000004  6859              LDR      r1,[r3,#4]
;;;142      
;;;143      /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
;;;144      tmpreg &= CLKCR_CLEAR_MASK;
000006  f64762ff          MOV      r2,#0x7eff
00000a  4391              BICS     r1,r1,r2
;;;145      
;;;146      /* Set CLKDIV bits according to SDIO_ClockDiv value */
;;;147      /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
;;;148      /* Set BYPASS bit according to SDIO_ClockBypass value */
;;;149      /* Set WIDBUS bits according to SDIO_BusWide value */
;;;150      /* Set NEGEDGE bits according to SDIO_ClockEdge value */
;;;151      /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
;;;152      tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
00000c  e9d05603          LDRD     r5,r6,[r0,#0xc]
000010  7802              LDRB     r2,[r0,#0]
000012  432a              ORRS     r2,r2,r5
000014  e9d05401          LDRD     r5,r4,[r0,#4]
000018  4334              ORRS     r4,r4,r6
00001a  4322              ORRS     r2,r2,r4
00001c  6940              LDR      r0,[r0,#0x14]
00001e  432a              ORRS     r2,r2,r5
000020  4302              ORRS     r2,r2,r0
000022  430a              ORRS     r2,r2,r1
;;;153                 SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
;;;154                 SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); 
;;;155      
;;;156      /* Write to SDIO CLKCR */
;;;157      SDIO->CLKCR = tmpreg;             
000024  605a              STR      r2,[r3,#4]
;;;158    }
000026  bd70              POP      {r4-r6,pc}
;;;159    
                          ENDP

                  |L19.40|
                          DCD      0x40018000