iolpc2470.h

lpc2478+ucosII+ucgui源码

typedef struct{
__REG32                 : 1;
__REG32 FUFRIS          : 1;
__REG32 LNBURIS         : 1;
__REG32 VCompRIS        : 1;
__REG32 BERRAW          : 1;
__REG32                 :27;
}__lcd_intraw_bits;

/* Masked Interrupt Status register */
typedef struct{
__REG32                 : 1;
__REG32 FUFMIS          : 1;
__REG32 LNBUMIS         : 1;
__REG32 VCompMIS        : 1;
__REG32 BERMIS          : 1;
__REG32                 :27;
}__lcd_intstat_bits;

/* Interrupt Clear register */
typedef struct{
__REG32                 : 1;
__REG32 FUFIC           : 1;
__REG32 LNBUIC          : 1;
__REG32 VCompIC         : 1;
__REG32 BERIC           : 1;
__REG32                 :27;
}__lcd_intclr_bits;

/* Cursor Control register */
typedef struct{
__REG32 CrsrOn          : 1;
__REG32                 : 3;
__REG32 CrsrNum         : 2;
__REG32                 :26;
}__crsr_ctrl_bits;

/* Cursor Configuration register */
typedef struct{
__REG32 CrsrSize        : 1;
__REG32 FrameSync       : 1;
__REG32                 :30;
}__crsr_cfg_bits;

/* Cursor Palette register 0 */
typedef struct{
__REG32 Red             : 8;
__REG32 Green           : 8;
__REG32 Blue            : 8;
__REG32                 : 8;
}__crsr_pal0_bits;

/* Cursor Palette register 1 */
typedef struct{
__REG32 Red             : 8;
__REG32 Green           : 8;
__REG32 Blue            : 8;
__REG32                 : 8;
}__crsr_pal1_bits;

/* Cursor XY Position register */
typedef struct{
__REG32 CrsrX           :10;
__REG32                 : 6;
__REG32 CrsrY           :10;
__REG32                 : 6;
}__crsr_xy_bits;

/* Cursor Clip Position register */
typedef struct{
__REG32 CrsrClipX       : 6;
__REG32                 : 2;
__REG32 CrsrClipY       : 6;
__REG32                 :18;
}__crsr_clip_bits;

/* Cursor Interrupt Mask register */
typedef struct{
__REG32 CrsrIM          : 1;
__REG32                 :31;
}__crsr_intmsk_bits;

/* Cursor Interrupt Clear register */
typedef struct{
__REG32 CrsrIC          : 1;
__REG32                 :31;
}__crsr_intclr_bits;

/* Cursor Raw Interrupt Status register */
typedef struct{
__REG32 CrsrRIS         : 1;
__REG32                 :31;
}__crsr_intraw_bits;

/* Cursor Masked Interrupt Status register */
typedef struct{
__REG32 CrsrMIS         : 1;
__REG32                 :31;
}__crsr_intstat_bits;

/* CAN acceptance filter mode register */
typedef struct {
  __REG32 ACCOFF          :1;
  __REG32 ACCBP           :1;
  __REG32 EFCAN           :1;
  __REG32                 :29;
} __afmr_bits;

/* CAN LUT Error Register */
typedef struct {
  __REG32 LUTERR          :1;
  __REG32                 :31;
} __luterr_bits;

/* Global FullCANInterrupt Enable register */
typedef struct {
  __REG32 FCANIE          :1;
  __REG32                 :31;
} __fcanie_bits;

/* FullCAN Interrupt and Capture registers 0 */
typedef struct {
  __REG32 INTPND0         :1;
  __REG32 INTPND1         :1;
  __REG32 INTPND2         :1;
  __REG32 INTPND3         :1;
  __REG32 INTPND4         :1;
  __REG32 INTPND5         :1;
  __REG32 INTPND6         :1;
  __REG32 INTPND7         :1;
  __REG32 INTPND8         :1;
  __REG32 INTPND9         :1;
  __REG32 INTPND10        :1;
  __REG32 INTPND11        :1;
  __REG32 INTPND12        :1;
  __REG32 INTPND13        :1;
  __REG32 INTPND14        :1;
  __REG32 INTPND15        :1;
  __REG32 INTPND16        :1;
  __REG32 INTPND17        :1;
  __REG32 INTPND18        :1;
  __REG32 INTPND19        :1;
  __REG32 INTPND20        :1;
  __REG32 INTPND21        :1;
  __REG32 INTPND22        :1;
  __REG32 INTPND23        :1;
  __REG32 INTPND24        :1;
  __REG32 INTPND25        :1;
  __REG32 INTPND26        :1;
  __REG32 INTPND27        :1;
  __REG32 INTPND28        :1;
  __REG32 INTPND29        :1;
  __REG32 INTPND30        :1;
  __REG32 INTPND31        :1;
} __fcanic0_bits;

/* FullCAN Interrupt and Capture registers 1 */
typedef struct {
  __REG32 INTPND32        :1;
  __REG32 INTPND33        :1;
  __REG32 INTPND34        :1;
  __REG32 INTPND35        :1;
  __REG32 INTPND36        :1;
  __REG32 INTPND37        :1;
  __REG32 INTPND38        :1;
  __REG32 INTPND39        :1;
  __REG32 INTPND40        :1;
  __REG32 INTPND41        :1;
  __REG32 INTPND42        :1;
  __REG32 INTPND43        :1;
  __REG32 INTPND44        :1;
  __REG32 INTPND45        :1;
  __REG32 INTPND46        :1;
  __REG32 INTPND47        :1;
  __REG32 INTPND48        :1;
  __REG32 INTPND49        :1;
  __REG32 INTPND50        :1;
  __REG32 INTPND51        :1;
  __REG32 INTPND52        :1;
  __REG32 INTPND53        :1;
  __REG32 INTPND54        :1;
  __REG32 INTPND55        :1;
  __REG32 INTPND56        :1;
  __REG32 INTPND57        :1;
  __REG32 INTPND58        :1;
  __REG32 INTPND59        :1;
  __REG32 INTPND60        :1;
  __REG32 INTPND61        :1;
  __REG32 INTPND62        :1;
  __REG32 INTPND63        :1;
} __fcanic1_bits;

/* CAN central transmit status register */
typedef struct {
  __REG32 TS1             : 1;
  __REG32 TS2             : 1;
  __REG32                 : 6;
  __REG32 TBS1            : 1;
  __REG32 TBS2            : 1;
  __REG32                 : 6;
  __REG32 TCS1            : 1;
  __REG32 TCS2            : 1;
  __REG32                 :14;
} __cantxsr_bits;

/* CAN central receive status register */
typedef struct {
  __REG32 RS1             : 1;
  __REG32 RS2             : 1;
  __REG32                 : 6;
  __REG32 RBS1            : 1;
  __REG32 RBS2            : 1;
  __REG32                 : 6;
  __REG32 DOS1            : 1;
  __REG32 DOS2            : 1;
  __REG32                 :14;
} __canrxsr_bits;

/* CAN miscellaneous status register */
typedef struct {
  __REG32 E1              : 1;
  __REG32 E2              : 1;
  __REG32                 : 6;
  __REG32 BS1             : 1;
  __REG32 BS2             : 1;
  __REG32                 :22;
} __canmsr_bits;

/* CAN mode register */
typedef struct {
  __REG32 RM              :1;
  __REG32 LOM             :1;
  __REG32 STM             :1;
  __REG32 TPM             :1;
  __REG32 SM              :1;
  __REG32 RPM             :1;
  __REG32                 :1;
  __REG32 TM              :1;
  __REG32                 :24;
} __canmod_bits;

/* CAN command register */
typedef struct {
  __REG32 TR              :1;
  __REG32 AT              :1;
  __REG32 RRB             :1;
  __REG32 CDO             :1;
  __REG32 SRR             :1;
  __REG32 STB1            :1;
  __REG32 STB2            :1;
  __REG32 STB3            :1;
  __REG32                 :24;
} __cancmr_bits;

/* CAN global status register */
typedef struct {
  __REG32 RBS              :1;
  __REG32 DOS              :1;
  __REG32 TBS              :1;
  __REG32 TCS              :1;
  __REG32 RS               :1;
  __REG32 TS               :1;
  __REG32 ES               :1;
  __REG32 BS               :1;
  __REG32                  :8;
  __REG32 RXERR            :8;
  __REG32 TXERR            :8;
} __cangsr_bits;

/* CAN interrupt capture register */
typedef struct {
  __REG32 RI               :1;
  __REG32 TI1              :1;
  __REG32 EI               :1;
  __REG32 DOI              :1;
  __REG32 WUI              :1;
  __REG32 EPI              :1;
  __REG32 ALI              :1;
  __REG32 BEI              :1;
  __REG32 IDI              :1;
  __REG32 TI2              :1;
  __REG32 TI3              :1;
  __REG32                  :5;
  __REG32 ERRBIT           :5;
  __REG32 ERRDIR           :1;
  __REG32 ERRC             :2;
  __REG32 ALCBIT           :8;
} __canicr_bits;

/* CAN interrupt enable register */
typedef struct {
  __REG32 RIE               :1;
  __REG32 TIE1              :1;
  __REG32 EIE               :1;
  __REG32 DOIE              :1;
  __REG32 WUIE              :1;
  __REG32 EPIE              :1;
  __REG32 ALIE              :1;
  __REG32 BEIE              :1;
  __REG32 IDIE              :1;
  __REG32 TIE2              :1;
  __REG32 TIE3              :1;
  __REG32                   :21;
} __canier_bits;

/* CAN bus timing register */
typedef struct {
  __REG32 BRP                :10;
  __REG32                    :4;
  __REG32 SJW                :2;
  __REG32 TSEG1              :4;
  __REG32 TSEG2              :3;
  __REG32 SAM                :1;
  __REG32                    :8;
} __canbtr_bits;

/* CAN error warning limit register */
typedef struct {
  __REG32 EWL                :8;
  __REG32                    :24;
} __canewl_bits;

/* CAN status register */
typedef struct {
  __REG32 RBS                :1;
  __REG32 DOS                :1;
  __REG32 TBS1               :1;
  __REG32 TCS1               :1;
  __REG32 RS                 :1;
  __REG32 TS1                :1;
  __REG32 ES                 :1;
  __REG32 BS                 :1;
  __REG32 /*RBS*/            :1;
  __REG32 /*DOS*/            :1;
  __REG32 TBS2               :1;
  __REG32 TCS2               :1;
  __REG32 /*RS*/             :1;
  __REG32 TS2                :1;
  __REG32 /*ES*/             :1;
  __REG32 /*BS*/             :1;
  __REG32 /*RBS*/            :1;
  __REG32 /*DOS*/            :1;
  __REG32 TBS3               :1;
  __REG32 TCS3               :1;
  __REG32 /*RS*/             :1;
  __REG32 TS3                :1;
  __REG32 /*ES*/             :1;
  __REG32 /*BS*/             :1;
  __REG32                    :8;
} __cansr_bits;

/* CAN rx frame status register */
typedef struct {
  __REG32 IDINDEX            :10;
  __REG32 BP                 :1;
  __REG32                    :5;
  __REG32 DLC                :4;
  __REG32                    :10;
  __REG32 RTR                :1;
  __REG32 FF                 :1;
} __canrfs_bits;

/* CAN rx identifier register */
typedef union {
  //CANxRID
  struct {
   __REG32 ID10_0             :11;
   __REG32                    :21;
  };
  //CANxRID
  struct {
   __REG32 ID29_18            :11;
   __REG32                    :21;
  };
  //CANxRID
  struct {
   __REG32 ID29_0             :29;
   __REG32                    :3;
  };
} __canrid_bits;

/* CAN rx data register A */
typedef struct {
  __REG32 DATA1               :8;
  __REG32 DATA2               :8;
  __REG32 DATA3               :8;
  __REG32 DATA4               :8;
} __canrda_bits;

/* CAN rx data register B */
typedef struct {
  __REG32 DATA5               :8;
  __REG32 DATA6               :8;
  __REG32 DATA7               :8;
  __REG32 DATA8               :8;
} __canrdb_bits;

/* CAN tx frame information register */
typedef struct {
  __REG32 PRIO              :8;
  __REG32                   :8;
  __REG32 DLC               :4;
  __REG32                   :10;
  __REG32 RTR               :1;
  __REG32 FF                :1;
} __cantfi_bits;

/* CAN tx identifier register */
typedef union {
  //CANxTIDy
  struct {
   __REG32 ID10_0             :11;
   __REG32                    :21;
  };
  //CANxTIDy
  struct {
   __REG32 ID29_18            :11;
   __REG32                    :21;
  };
  //CANxTIDy
  struct {
   __REG32 ID29_0             :29;
   __REG32                    :3;
  };
} __cantid_bits;

/* CAN tx data register A */
typedef struct {
  __REG32 DATA1               :8;
  __REG32 DATA2               :8;
  __REG32 DATA3               :8;
  __REG32 DATA4               :8;
} __cantda_bits;

/* CAN tx data register B */
typedef struct {
  __REG32 DATA5               :8;
  __REG32 DATA6               :8;
  __REG32 DATA7               :8;
  __REG32 DATA8               :8;
} __cantdb_bits;

/* USB - Device Interrupt Status Register */
/* OTG_status and control Register */
typedef union {
// USBPORTSEL
  struct {
  __REG32 PORTSEL           : 2;
  __REG32                   :30;
  };
// OTGSTCTRL
  struct {
__REG32 PORT_FUNC           : 2;
__REG32 TMR_SCALE           : 2;
__REG32 TMR_MODE            : 1;
__REG32 TMR_EN              : 1;
__REG32 TMR_RST             : 1;
__REG32                     : 1;
__REG32 B_HNP_TRACK         : 1;
__REG32 A_HNP_TRACK         : 1;
__REG32 PU_REMOVED          : 1;
__REG32                     : 5;
__REG32 TMR_CNT             :16;
  };
} __usbportsel_bits;

/* USB Clock Control register (USBClkCtrl - 0xFFE0 CFF4) */
/* OTG_clock Registers */
typedef union {
  // USBCLKCTRL
  struct{
__REG32                 : 1;
__REG32 DEV_CLK_EN      : 1;
__REG32                 : 1;
__REG32 PORTSEL_CLK_EN  : 1;
__REG32 AHB_CLK_EN      : 1;
__REG32                 :27;
  };
  // OTGCLKCTRL
  struct{
__REG32 _HOST_CLK_EN  : 1;
__REG32 _DEV_CLK_EN   : 1;
__REG32 _I2C_CLK_EN   : 1;
__REG32 _OTG_CLK_EN   : 1;
__REG32 _AHB_CLK_EN   : 1;
__REG32               :27;
  };
} __usbclkctrl_bits;


/* USB Clock Status register (USBClkSt - 0xFFE0 CFF8) */
/* OTG_status Registers */
typedef union {
  // USBCLKST
  struct{
__REG32                 : 1;
__REG32 DEV_CLK_ON      : 1;
__REG32                 : 1;
__REG32 PORTSEL_CLK_ON  : 1;
__REG32 AHB_CLK_ON      : 1;
__REG32                 :27;
  };
  // OTGCLKST
  struct{
__REG32 _HOST_CLK_ON : 1;
__REG32 _DEV_CLK_ON  : 1;
__REG32 _I2C_CLK_ON  : 1;
__REG32 _OTG_CLK_ON  : 1;
__REG32 _AHB_CLK_ON  : 1;
__REG32              :27;
  };
} __usbclkst_bits;

/* USB - Device Interrupt Status Register */
typedef struct {
  __REG32 USB_INT_REQ_LP    : 1;
  __REG32 USB_INT_REQ_HP    : 1;
  __REG32 USB_INT_REQ_DMA   : 1;
  __REG32 USB_HOST_INT      : 1;
  __REG32 USB_ATX_INT       : 1;
  __REG32 USB_OTG_INT       : 1;
  __REG32 USB_I2C_INT       : 1;
  __REG32                   : 1;
  __REG32 USB_NEED_CLOCK    : 1;
  __REG32                   :22;
  __REG32 EN_USB_INTS       : 1;
} __usbints_bits;

/* USB - Device Interrupt Status Register */
/* USB - Device Interrupt Enable Register */
/* USB - Device Interrupt Clear Register */
/* USB - Device Interrupt Set Register */
typedef struct {
  __REG32 FRAME             : 1;
  __REG32 EP_FAST           : 1;
  __REG32 EP_SLOW           : 1;
  __REG32 DEV_STAT          : 1;
  __REG32 CCEMTY            : 1;
  __REG32 CDFULL            : 1;
  __REG32 RXENDPKT          : 1;
  __REG32 TXENDPKT          : 1;
  __REG32 EP_RLZED          : 1;
  __REG32 ERR_INT           : 1;
  __REG32                   :22;
} __usbdevintst_bits;

/* USB - Device Interrupt Priority Register */
typedef struct {
  __REG8  FRAME             : 1;
  __REG8  EP_FAST           : 1;
  __REG8                    : 6;
} __usbdevintpri_bits;

/* USB - Endpoint Interrupt Status Register */
/* USB - Endpoint Interrupt Enable Register */
/* USB - Endpoint Interrupt Clear Register */
/* USB - Endpoint Interrupt Set Register *