iolpc2470.h
来自「lpc2478+ucosII+ucgui源码」· C头文件 代码 · 共 2,785 行 · 第 1/5 页
H
2,785 行
//FIO4PIN2
//FIO4SET2
//FIO4CLR2
struct{
__REG8 P4_0 : 1;
__REG8 P4_1 : 1;
__REG8 P4_2 : 1;
__REG8 P4_3 : 1;
__REG8 P4_4 : 1;
__REG8 P4_5 : 1;
__REG8 P4_6 : 1;
__REG8 P4_7 : 1;
} __byte2_bit;
__REG8 __byte2;
};
union
{
//FIO4DIR3
//FIO4MASK3
//FIO4PIN3
//FIO4SET3
//FIO4CLR3
struct{
__REG8 P4_0 : 1;
__REG8 P4_1 : 1;
__REG8 P4_2 : 1;
__REG8 P4_3 : 1;
__REG8 P4_4 : 1;
__REG8 P4_5 : 1;
__REG8 P4_6 : 1;
__REG8 P4_7 : 1;
} __byte3_bit;
__REG8 __byte3;
};
};
struct
{
union
{
//FIO4DIRL
//FIO4MASKL
//FIO4PINL
//FIO4SETL
//FIO4CLRL
struct{
__REG16 P4_0 : 1;
__REG16 P4_1 : 1;
__REG16 P4_2 : 1;
__REG16 P4_3 : 1;
__REG16 P4_4 : 1;
__REG16 P4_5 : 1;
__REG16 P4_6 : 1;
__REG16 P4_7 : 1;
__REG16 P4_8 : 1;
__REG16 P4_9 : 1;
__REG16 P4_10 : 1;
__REG16 P4_11 : 1;
__REG16 P4_12 : 1;
__REG16 P4_13 : 1;
__REG16 P4_14 : 1;
__REG16 P4_15 : 1;
} __shortl_bit;
__REG16 __shortl;
};
union
{
//FIO4DIRU
//FIO4MASKU
//FIO4PINU
//FIO4SETU
//FIO4CLRU
struct{
__REG16 P4_0 : 1;
__REG16 P4_1 : 1;
__REG16 P4_2 : 1;
__REG16 P4_3 : 1;
__REG16 P4_4 : 1;
__REG16 P4_5 : 1;
__REG16 P4_6 : 1;
__REG16 P4_7 : 1;
__REG16 P4_8 : 1;
__REG16 P4_9 : 1;
__REG16 P4_10 : 1;
__REG16 P4_11 : 1;
__REG16 P4_12 : 1;
__REG16 P4_13 : 1;
__REG16 P4_14 : 1;
__REG16 P4_15 : 1;
} __shortu_bit;
__REG16 __shortu;
};
};
} __fgpio4_bits;
/* GPIO overall Interrupt Status register */
typedef struct{
__REG32 P0INT : 1;
__REG32 : 1;
__REG32 P2INT : 1;
__REG32 :29;
}__iointst_bits;
/* MAC Configuration Register 1 */
typedef struct{
__REG32 RE : 1;
__REG32 PARF : 1;
__REG32 RXFC : 1;
__REG32 TXFC : 1;
__REG32 LB : 1;
__REG32 : 3;
__REG32 RSTTX : 1;
__REG32 RSTMCSTX : 1;
__REG32 RSTRX : 1;
__REG32 RSTMCSRX : 1;
__REG32 : 2;
__REG32 SIMRST : 1;
__REG32 SOFTRST : 1;
__REG32 :16;
}__mac1_bits;
/* MAC Configuration Register 2 */
typedef struct{
__REG32 FD : 1;
__REG32 FLC : 1;
__REG32 HFE : 1;
__REG32 DLYCRC : 1;
__REG32 CRCEN : 1;
__REG32 PADCRCEN : 1;
__REG32 VLANCRCEN : 1;
__REG32 ADPE : 1;
__REG32 PPE : 1;
__REG32 LPE : 1;
__REG32 : 2;
__REG32 NB : 1;
__REG32 BP : 1;
__REG32 ED : 1;
__REG32 :17;
}__mac2_bits;
/* Back-to-Back Inter-Packet-Gap Register */
typedef struct{
__REG32 IPG : 7;
__REG32 :25;
}__ipgt_bits;
/* Non Back-to-Back Inter-Packet-Gap Register */
typedef struct{
__REG32 IPGR2 : 7;
__REG32 : 1;
__REG32 IPGR1 : 7;
__REG32 :17;
}__ipgr_bits;
/*Collision Window / Retry Register */
typedef struct{
__REG32 RM : 4;
__REG32 : 4;
__REG32 CW : 6;
__REG32 :18;
}__clrt_bits;
/* Maximum Frame Register */
typedef struct{
__REG32 MAXF :16;
__REG32 :16;
}__maxf_bits;
/* PHY Support Register */
typedef struct{
__REG32 : 8;
__REG32 SPEED : 1;
__REG32 :23;
}__supp_bits;
/* Test Register */
typedef struct{
__REG32 SPQ : 1;
__REG32 TP : 1;
__REG32 TB : 1;
__REG32 :29;
}__test_bits;
/* MII Mgmt Configuration Register */
typedef struct{
__REG32 SI : 1;
__REG32 SP : 1;
__REG32 CS : 3;
__REG32 :10;
__REG32 RSTMIIMGMT : 1;
__REG32 :16;
}__mcfg_bits;
/* MII Mgmt Command Register */
typedef struct{
__REG32 READ : 1;
__REG32 SCAN : 1;
__REG32 :30;
}__mcmd_bits;
/* MII Mgmt Address Register */
typedef struct{
__REG32 REGADDR : 5;
__REG32 : 3;
__REG32 PHY_ADDR : 5;
__REG32 :19;
}__madr_bits;
/* MII Mgmt Write Data Register */
typedef struct{
__REG32 WRITEDATA :16;
__REG32 :16;
}__mwtd_bits;
/* MII Mgmt Read Data Register */
typedef struct{
__REG32 READDATA :16;
__REG32 :16;
}__mrdd_bits;
/* MII Mgmt Indicators Register */
typedef struct{
__REG32 BUSY : 1;
__REG32 SCANNING : 1;
__REG32 NOT_VALID : 1;
__REG32 MII_LINK_FAIL : 1;
__REG32 :28;
}__mind_bits;
/* Station Address 0 Register */
typedef struct{
__REG32 STATION_ADDR_2 : 8;
__REG32 STATION_ADDR_1 : 8;
__REG32 :16;
}__sa0_bits;
/* Station Address 1 Register */
typedef struct{
__REG32 STATION_ADDR_4 : 8;
__REG32 STATION_ADDR_3 : 8;
__REG32 :16;
}__sa1_bits;
/* Station Address 2 Register */
typedef struct{
__REG32 STATION_ADDR_6 : 8;
__REG32 STATION_ADDR_5 : 8;
__REG32 :16;
}__sa2_bits;
/* Command Register */
typedef struct{
__REG32 RXENABLE : 1;
__REG32 TXENABLE : 1;
__REG32 : 1;
__REG32 REGRESET : 1;
__REG32 TXRESET : 1;
__REG32 RXRESET : 1;
__REG32 PASSRUNTFRAME : 1;
__REG32 PASSRXFILTER : 1;
__REG32 TXFLOWCONTROL : 1;
__REG32 RMII : 1;
__REG32 FULLDUPLEX : 1;
__REG32 :21;
}__command_bits;
/* Status Register */
typedef struct{
__REG32 RXSTATUS : 1;
__REG32 TXSTATUS : 1;
__REG32 :30;
}__status_bits;
/* Receive Number of Descriptors Register */
typedef struct{
__REG32 RXDESCRIPTORNUMBER :16;
__REG32 :16;
}__rxdescrn_bits;
/* Receive Produce Index Register */
typedef struct{
__REG32 RXPRODUCDINDEX :16;
__REG32 :16;
}__rxprodind_bits;
/* Receive Consume Index Register */
typedef struct{
__REG32 RXCONSUMEINDEX :16;
__REG32 :16;
}__rxcomind_bits;
/* Transmit Number of Descriptors Register */
typedef struct{
__REG32 TXDESCRIPTORNUMBER :16;
__REG32 :16;
}__txdescrn_bits;
/* Transmit Produce Index Register */
typedef struct{
__REG32 TXPRODUCDINDEX :16;
__REG32 :16;
}__txprodind_bits;
/* Transmit Consume Index Register */
typedef struct{
__REG32 TXCONSUMEINDEX :16;
__REG32 :16;
}__txcomind_bits;
/* Transmit Status Vector 0 Register */
typedef struct{
__REG32 CCR_ERR : 1;
__REG32 LCERR : 1;
__REG32 LOOR : 1;
__REG32 DONE : 1;
__REG32 MULTICAST : 1;
__REG32 BROADCAST : 1;
__REG32 PD : 1;
__REG32 ED : 1;
__REG32 EC : 1;
__REG32 LC : 1;
__REG32 GIANT : 1;
__REG32 UNDERRUN : 1;
__REG32 TB :16;
__REG32 CF : 1;
__REG32 PAUSE : 1;
__REG32 BACKPRESSURE : 1;
__REG32 VLAN : 1;
}__tsv0_bits;
/* Transmit Status Vector 1 Register */
typedef struct{
__REG32 TBC :16;
__REG32 TCC : 4;
__REG32 :12;
}__tsv1_bits;
/* Receive Status Vector Register */
typedef struct{
__REG32 RBC :16;
__REG32 PPI : 1;
__REG32 RXDVEPS : 1;
__REG32 CEPS : 1;
__REG32 RCV : 1;
__REG32 CRC_ERR : 1;
__REG32 LCE : 1;
__REG32 LOOR : 1;
__REG32 R_OK : 1;
__REG32 MULTICAST : 1;
__REG32 BROADCAST : 1;
__REG32 DN : 1;
__REG32 CF : 1;
__REG32 PAUSE : 1;
__REG32 UO : 1;
__REG32 VLAN : 1;
__REG32 : 1;
}__rsv_bits;
/* Flow Control Counter Register */
typedef struct{
__REG32 MC :16;
__REG32 PT :16;
}__fwctrlcnt_bits;
/* Flow Control Status Register */
typedef struct{
__REG32 MCC :16;
__REG32 :16;
}__fwctrlstat_bits;
/* Receive Filter Control Register */
typedef struct{
__REG32 AUE : 1;
__REG32 ABE : 1;
__REG32 AME : 1;
__REG32 AUHE : 1;
__REG32 AMHE : 1;
__REG32 APE : 1;
__REG32 : 6;
__REG32 MPEWOL : 1;
__REG32 RXFEWOL : 1;
__REG32 :18;
}__rxflctrl_bits;
/* Receive Filter WoL Status Register */
typedef struct{
__REG32 AUWOL : 1;
__REG32 ABWOL : 1;
__REG32 AMWOL : 1;
__REG32 AUHWOL : 1;
__REG32 AMHWOL : 1;
__REG32 APWOL : 1;
__REG32 : 1;
__REG32 RXFWOL : 1;
__REG32 MPWOL : 1;
__REG32 :23;
}__rxflwolstat_bits;
/* Receive Filter WoL Clear Register */
typedef struct{
__REG32 AUWOLC : 1;
__REG32 ABWOLC : 1;
__REG32 AMWOLC : 1;
__REG32 AUHWOLC : 1;
__REG32 AMHWOLC : 1;
__REG32 APWOLC : 1;
__REG32 : 1;
__REG32 RXFWOLC : 1;
__REG32 MPWOLC : 1;
__REG32 :23;
}__rxflwolclr_bits;
/* Interrupt Status Register */
typedef struct{
__REG32 RXOVERRUNINT : 1;
__REG32 RXERRORINT : 1;
__REG32 RXFINISHEDINT : 1;
__REG32 RXDONEINT : 1;
__REG32 TXUNDERRUNINT : 1;
__REG32 TXERRORINT : 1;
__REG32 TXFINISHEDINT : 1;
__REG32 TXDONEINT : 1;
__REG32 : 4;
__REG32 SOFTINT : 1;
__REG32 WAKEUPINT : 1;
__REG32 :18;
}__intstat_bits;
/* Interrupt Enable Register */
typedef struct{
__REG32 RXOVERRUNINTEN : 1;
__REG32 RXERRORINTEN : 1;
__REG32 RXFINISHEDINTEN : 1;
__REG32 RXDONEINTEN : 1;
__REG32 TXUNDERRUNINTEN : 1;
__REG32 TXERRORINTEN : 1;
__REG32 TXFINISHEDINTEN : 1;
__REG32 TXDONEINTEN : 1;
__REG32 : 4;
__REG32 SOFTINTEN : 1;
__REG32 WAKEUPINTEN : 1;
__REG32 :18;
}__intena_bits;
/* Interrupt Clear Register */
typedef struct{
__REG32 RXOVERRUNINTCLR : 1;
__REG32 RXERRORINTCLR : 1;
__REG32 RXFINISHEDINTCLR: 1;
__REG32 RXDONEINTCLR : 1;
__REG32 TXUNDERRUNINTCLR: 1;
__REG32 TXERRORINTCLR : 1;
__REG32 TXFINISHEDINTCLR: 1;
__REG32 TXDONEINTCLR : 1;
__REG32 : 4;
__REG32 SOFTINTCLR : 1;
__REG32 WAKEUPINTCLR : 1;
__REG32 :18;
}__intclr_bits;
/* Interrupt Set Register */
typedef struct{
__REG32 RXOVERRUNINTSET : 1;
__REG32 RXERRORINTSET : 1;
__REG32 RXFINISHEDINTSET: 1;
__REG32 RXDONEINTSET : 1;
__REG32 TXUNDERRUNINTSET: 1;
__REG32 TXERRORINTSET : 1;
__REG32 TXFINISHEDINTSET: 1;
__REG32 TXDONEINTSET : 1;
__REG32 : 4;
__REG32 SOFTINTSET : 1;
__REG32 WAKEUPINTSET : 1;
__REG32 :18;
}__intset_bits;
/* Power Down Register */
typedef struct{
__REG32 :31;
__REG32 POWERDOWN : 1;
}__pwrdn_bits;
/* LCD Configuration register */
typedef struct{
__REG32 CLKDIV : 5;
__REG32 :27;
}__lcd_cfg_bits;
/* Horizontal Timing register */
typedef struct{
__REG32 : 2;
__REG32 PPL : 6;
__REG32 HSW : 8;
__REG32 HFP : 8;
__REG32 HBP : 8;
}__lcd_timh_bits;
/* Vertical Timing register */
typedef struct{
__REG32 LPP :10;
__REG32 VSW : 6;
__REG32 VFP : 8;
__REG32 VBP : 8;
}__lcd_timv_bits;
/* Clock and Signal Polarity register */
typedef struct{
__REG32 PCD_LO : 5;
__REG32 CLKSEL : 1;
__REG32 ACB : 5;
__REG32 IVS : 1;
__REG32 IHS : 1;
__REG32 IPC : 1;
__REG32 IOE : 1;
__REG32 : 1;
__REG32 CPL :10;
__REG32 BCD : 1;
__REG32 PCD_HI : 5;
}__lcd_pol_bits;
/* Line End Control register */
typedef struct{
__REG32 LED : 7;
__REG32 : 9;
__REG32 LEE : 1;
__REG32 :15;
}__lcd_le_bits;
/* LCD Control register */
typedef struct{
__REG32 LcdEn : 1;
__REG32 LcdBpp : 3;
__REG32 LcdBW : 1;
__REG32 LcdTFT : 1;
__REG32 LcdMono8 : 1;
__REG32 LcdDual : 1;
__REG32 BGR : 1;
__REG32 BEBO : 1;
__REG32 BEPO : 1;
__REG32 LcdPwr : 1;
__REG32 LcdVComp : 2;
__REG32 : 2;
__REG32 WATERMARK : 1;
__REG32 :15;
}__lcd_ctrl_bits;
/* Interrupt Mask register */
typedef struct{
__REG32 : 1;
__REG32 FUFIM : 1;
__REG32 LNBUIM : 1;
__REG32 VCompIM : 1;
__REG32 BERIM : 1;
__REG32 :27;
}__lcd_intmsk_bits;
/* Raw Interrupt Status register */
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