iolpc2470.h

lpc2478+ucosII+ucgui源码

/***************************************************************************
 **
 **    This file defines the Special Function Registers for
 **    NXP LPC2470
 **
 **    Used with ARM IAR C/C++ Compiler and Assembler.
 **
 **    (c) Copyright IAR Systems 2006
 **
 **    $Revision: 22899 $
 **
 **    Note: Only little endian addressing of 8 bit registers.
 ***************************************************************************/

#ifndef __IOLPC2470_H
#define __IOLPC2470_H

#if (((__TID__ >> 8) & 0x7F) != 0x4F)     /* 0x4F = 79 dec */
#error This file should only be compiled by ARM IAR compiler and assembler
#endif

#include "io_macros.h"

/***************************************************************************
 ***************************************************************************
 **
 **    LPC2470 SPECIAL FUNCTION REGISTERS
 **
 ***************************************************************************
 ***************************************************************************
 ***************************************************************************/

/* C-compiler specific declarations  ***************************************/
#ifdef __IAR_SYSTEMS_ICC__

#ifndef _SYSTEM_BUILD
#pragma system_include
#endif

#if __LITTLE_ENDIAN__ == 0
#error This file should only be compiled in little endian mode
#endif

/* Memory mapping control register */
typedef struct{
__REG32 MAP         : 2;
__REG32             :30;
} __memmap_bits;

/* Reset Source Identification Register */
typedef struct{
__REG32 POR         : 1;
__REG32 EXTR        : 1;
__REG32 WDTR        : 1;
__REG32 BODR        : 1;
__REG32             :28;
} __rsir_bits;

/* External interrupt register */
typedef struct{
__REG32 EINT0       : 1;
__REG32 EINT1       : 1;
__REG32 EINT2       : 1;
__REG32 EINT3       : 1;
__REG32             :28;
} __extint_bits;

/* External Interrupt Mode Register */
typedef struct{
__REG32 EXTMODE0    : 1;
__REG32 EXTMODE1    : 1;
__REG32 EXTMODE2    : 1;
__REG32 EXTMODE3    : 1;
__REG32             :28;
} __extmode_bits;

/* External Interrupt Polarity Register */
typedef struct{
__REG32 EXTPOLAR0   : 1;
__REG32 EXTPOLAR1   : 1;
__REG32 EXTPOLAR2   : 1;
__REG32 EXTPOLAR3   : 1;
__REG32             :28;
} __extpolar_bits;

/* System Controls and Status register */
typedef struct{
__REG32 GPIOM       : 1;
__REG32 EMCRD       : 1;
__REG32             : 1;
__REG32 MCIPWR      : 1;
__REG32 OSCRANGE    : 1;
__REG32 OSCEN       : 1;
__REG32 OSCSTAT     : 1;
__REG32             :25;
} __scs_bits;

/* AHB Arbiter Configuration Register*/
typedef struct{
__REG32 SHDL        : 1;
__REG32 BB          : 2;
__REG32 QT          : 1;
__REG32 QS          : 4;
__REG32 DM          : 4;
__REG32 EP1         : 4;
__REG32 EP2         : 4;
__REG32 EP3         : 4;
__REG32 EP4         : 4;
__REG32             : 4;
} __ahbcfg1_bits;

typedef struct{
__REG32 SHDL        : 1;
__REG32 BB          : 2;
__REG32 QT          : 1;
__REG32 QS          : 4;
__REG32 DM          : 4;
__REG32 EP1         : 4;
__REG32 EP2         : 4;
__REG32             :12;
} __ahbcfg2_bits;

/* Clock Soucre Select register */
typedef struct{
__REG32 CLKSRC      : 2;
__REG32             :30;
} __clksrcsel_bits;

/* IRC Trim Register (IRCTRIM - 0xE01FC1A4) */
typedef struct{
__REG32 IRCTRIM     : 8;
__REG32             :24;
} __irctrim_bits;

/* CPU Clock Configuration register */
typedef struct{
__REG32 CCLKSEL     : 8;
__REG32             :24;
} __cclkcfg_bits;

/* USB Clock Configuration register */
typedef struct{
__REG32 USBSEL      : 4;
__REG32             :28;
} __usbclkcfg_bits;

/* Peripheral Clock Selection registers 0 */
typedef struct{
__REG32 PCLK_WDT    : 2;
__REG32 PCLK_TIMER0 : 2;
__REG32 PCLK_TIMER1 : 2;
__REG32 PCLK_UART0  : 2;
__REG32 PCLK_UART1  : 2;
__REG32 PCLK_PWM0   : 2;
__REG32 PCLK_PWM1   : 2;
__REG32 PCLK_I2C0   : 2;
__REG32 PCLK_SPI    : 2;
__REG32 PCLK_RTC    : 2;
__REG32 PCLK_SSP1   : 2;
__REG32 PCLK_DAC    : 2;
__REG32 PCLK_ADC    : 2;
__REG32 PCLK_CAN1   : 2;
__REG32 PCLK_CAN2   : 2;
__REG32 PCLK_ACF    : 2;
} __pclksel0_bits;

/* Peripheral Clock Selection registers 1 */
typedef struct{
__REG32 PCLK_BAT_RAM: 2;
__REG32 PCLK_GPIO   : 2;
__REG32 PCLK_PCB    : 2;
__REG32 PCLK_I2C1   : 2;
__REG32             : 2;
__REG32 PCLK_SSP0   : 2;
__REG32 PCLK_TIMER2 : 2;
__REG32 PCLK_TIMER3 : 2;
__REG32 PCLK_UART2  : 2;
__REG32 PCLK_UART3  : 2;
__REG32 PCLK_I2C2   : 2;
__REG32 PCLK_I2S    : 2;
__REG32 PCLK_MCI    : 2;
__REG32             : 2;
__REG32 PCLK_SYSCON : 2;
__REG32             : 2;
} __pclksel1_bits;

/* PLL control register */
typedef struct{
__REG32 PLLE        : 1;
__REG32 PLLC        : 1;
__REG32             :30;
} __pllcon_bits;

/* PLL config register */
typedef struct{
__REG32 MSEL        :15;
__REG32             : 1;
__REG32 NSEL        : 8;
__REG32             : 8;
} __pllcfg_bits;

/* PLL status register */
typedef struct{
__REG32 MSEL        :15;
__REG32             : 1;
__REG32 NSEL        : 8;
__REG32 PLLE        : 1;
__REG32 PLLC        : 1;
__REG32 PLOCK       : 1;
__REG32             : 5;
} __pllstat_bits;

/* PLL feed register */
typedef struct{
__REG32 FEED        : 8;
__REG32             :24;
} __pllfeed_bits;

/* Power control register */
typedef struct{
__REG32 IDL         : 1;
__REG32 PD          : 1;
__REG32 BODPDM      : 1;
__REG32 BOGD        : 1;
__REG32 BORD        : 1;
__REG32             : 2;
__REG32 PM2         : 1;
__REG32             :24;
}__pcon_bits;

/* Interrupt Wakeup Register */
typedef struct{
__REG32 EXTWAKE0    : 1;
__REG32 EXTWAKE1    : 1;
__REG32 EXTWAKE2    : 1;
__REG32 EXTWAKE3    : 1;
__REG32 ETHWAK      : 1;
__REG32 USBWAKE     : 1;
__REG32 CANWAKE     : 1;
__REG32 GPIO0WAKE   : 1;
__REG32 GPIO2WAKE   : 1;
__REG32             : 5;
__REG32 BODWAKE     : 1;
__REG32 RTCWAKE     : 1;
__REG32             :16;
}__intwake_bits;

/* Power control for peripherals register */
typedef struct{
__REG32             : 1;
__REG32 PCTIM0      : 1;
__REG32 PCTIM1      : 1;
__REG32 PCUART0     : 1;
__REG32 PCUART1     : 1;
__REG32 PCPWM0      : 1;
__REG32 PCPWM1      : 1;
__REG32 PCI2C0      : 1;
__REG32 PCSPI       : 1;
__REG32 PCRTC       : 1;
__REG32 PCSSP1      : 1;
__REG32 PCEMC       : 1;
__REG32 PCAD        : 1;
__REG32 PCAN1       : 1;
__REG32 PCAN2       : 1;
__REG32             : 4;
__REG32 PCI2C1      : 1;
__REG32 PCLCD       : 1;
__REG32 PCSSP0      : 1;
__REG32 PCTIM2      : 1;
__REG32 PCTIM3      : 1;
__REG32 PCUART2     : 1;
__REG32 PCUART3     : 1;
__REG32 PCI2C2      : 1;
__REG32 PCI2S       : 1;
__REG32 PCSDC       : 1;
__REG32 PCGPDMA     : 1;
__REG32 PCENET      : 1;
__REG32 PCUSB       : 1;
} __pconp_bits;

/* Memory accelerator module control register */
typedef struct {
  __REG32 MODECTRL  : 2;
  __REG32           :30;
} __mamcr_bits;

/* Memory accelerator module timing register */
typedef struct {
  __REG32 CYCLES    : 3;
  __REG32           :29;
} __mamtim_bits;

/* EMC Control Register */
typedef struct {
  __REG32 E         : 1;
  __REG32 M         : 1;
  __REG32 L         : 1;
  __REG32           :29;
} __emc_ctrl_bits;

/* EMC Status Register */
typedef struct {
  __REG32 B         : 1;
  __REG32 S         : 1;
  __REG32 SA        : 1;
  __REG32           :29;
} __emc_st_bits;

/* EMC Configuration Register */
typedef struct {
  __REG32 ENDIAN    : 1;
  __REG32           :31;
} __emc_cfg_bits;

/* Dynamic Memory Control Register */
typedef struct {
  __REG32 CE        : 1;
  __REG32 CS        : 1;
  __REG32 SR        : 1;
  __REG32           : 2;
  __REG32 MMC       : 1;
  __REG32           : 1;
  __REG32 I         : 2;
  __REG32           : 4;
  __REG32 DP        : 1;
  __REG32           :18;
} __emc_dctrl_bits;

/* Dynamic Memory Refresh Timer Register */
typedef struct {
  __REG32 REFRESH   :11;
  __REG32           :21;
} __emc_drfr_bits;

/* Dynamic Memory Read Configuration Register */
typedef struct {
  __REG32 RD        : 2;
  __REG32           :30;
} __emc_drdcfg_bits;

/* Dynamic Memory Percentage Command Period Register */
typedef struct {
  __REG32 PR        : 4;
  __REG32           :28;
} __emc_drp_bits;

/* Dynamic Memory Active to Precharge Command Period Register */
typedef struct {
  __REG32 RAS       : 4;
  __REG32           :28;
} __emc_dras_bits;

/* Dynamic Memory Self-refresh Exit Time Register */
typedef struct {
  __REG32 SREX      : 4;
  __REG32           :28;
} __emc_dsrex_bits;

/* Dynamic Memory Last Data Out to Active Time Register */
typedef struct {
  __REG32 APR       : 4;
  __REG32           :28;
} __emc_dapr_bits;

/* Dynamic Memory Data-in to Active Command Time Register */
typedef struct {
  __REG32 DAL       : 4;
  __REG32           :28;
} __emc_ddal_bits;

/* Dynamic Memory Write Recovery Time Register */
typedef struct {
  __REG32 WR        : 4;
  __REG32           :28;
} __emc_dwr_bits;

/* Dynamic Memory Active to Active Command Period Register */
typedef struct {
  __REG32 RC        : 5;
  __REG32           :27;
} __emc_drc_bits;

/* Dynamic Memory Auto-refresh Period Register */
typedef struct {
  __REG32 RFC       : 5;
  __REG32           :27;
} __emc_drfc_bits;

/* Dynamic Memory Exit Self-refresh Register */
typedef struct {
  __REG32 XSR       : 5;
  __REG32           :27;
} __emc_dxsr_bits;

/* Dynamic Memory Active Bank A to Active Bank B Time Register */
typedef struct {
  __REG32 RRD       : 4;
  __REG32           :28;
} __emc_drrd_bits;

/* Dynamic Memory Load Mode Register to Active Command Time */
typedef struct {
  __REG32 MRD       : 4;
  __REG32           :28;
} __emc_dmrd_bits;

/* Dynamic Memory Configuration Registers */
typedef struct {
  __REG32           : 3;
  __REG32 MD        : 2;
  __REG32           : 2;
  __REG32 AML       : 6;
  __REG32           : 1;
  __REG32 AMH       : 1;
  __REG32           : 4;
  __REG32 B         : 1;
  __REG32 P         : 1;
  __REG32           :11;
} __emc_d_config_bits;

/* Dynamic Memory RAS & CAS Delay Registers */
typedef struct {
  __REG32 RAS       : 2;
  __REG32           : 6;
  __REG32 CAS       : 2;
  __REG32           :22;
} __emc_d_ras_cas_bits;

/* Static Memory Configuration Registers */
typedef struct {
  __REG32 MW        : 2;
  __REG32           : 1;
  __REG32 PM        : 1;
  __REG32           : 2;
  __REG32 PC        : 1;
  __REG32 PB        : 1;
  __REG32 EW        : 1;
  __REG32           :10;
  __REG32 B         : 1;
  __REG32 P         : 1;
  __REG32           :11;
} __emc_s_config_bits;

/* Static Memory Write Enable Delay Registers */
typedef struct {
  __REG32 WAITWEN   : 4;
  __REG32           :28;
} __emc_s_wait_wen_bits;

/* Static Memory Output Enable Delay Registers */
typedef struct {
  __REG32 WAITOEN   : 4;
  __REG32           :28;
} __emc_s_wait_oen_bits;

/* Static Memory Read Delay Registers */
typedef struct {
  __REG32 WAITRD    : 5;
  __REG32           :27;
} __emc_s_wait_rd_bits;

/* Static Memory Page Mode Read Delay Registers */
typedef struct {
  __REG32 WAITPAGE  : 5;
  __REG32           :27;
} __emc_s_wait_pg_bits;

/* Static Memory Write Delay Registers */
typedef struct {
  __REG32 WAITWR    : 5;
  __REG32           :27;
} __emc_s_wait_wr_bits;

/* Static Memory Extended Wait Register */
typedef struct {
  __REG32 EXTENDEDWAIT  :10;
  __REG32               :22;
} __emc_s_ext_wait_bits;

/* Static Memory Turn Round Delay Registers */
typedef struct {
  __REG32 WAITTURN  : 4;
  __REG32           :28;
} __emc_s_wait_turn_bits;

/* VIC Interrupt registers */
typedef struct{
__REG32 WDT       : 1;
__REG32           : 1;
__REG32 ARMCORE0  : 1;
__REG32 ARMCORE1  : 1;
__REG32 TIMER0    : 1;
__REG32 TIMER1    : 1;
__REG32 UART0     : 1;
__REG32 UART1     : 1;
__REG32 PWM01     : 1;
__REG32 I2C0      : 1;
__REG32 SPI       : 1;
__REG32 SSP1      : 1;
__REG32 PLL       : 1;
__REG32 RTC       : 1;
__REG32 EINT0     : 1;
__REG32 EINT1     : 1;
__REG32 EINT2     : 1;
__REG32 EINT3     : 1;
__REG32 AD0       : 1;
__REG32 I2C1      : 1;
__REG32 BOD       : 1;
__REG32 ETHERNET  : 1;
__REG32 USB       : 1;
__REG32 CAN12     : 1;
__REG32 SDMMC     : 1;
__REG32 GPDMA     : 1;
__REG32 TIMER2    : 1;
__REG32 TIMER3    : 1;
__REG32 UART2     : 1;
__REG32 UART3     : 1;
__REG32 I2C2      : 1;
__REG32 I2S       : 1;
} __vicint_bits;

/* VIC Vector control registers */
typedef struct{
__REG32 PRIORITY : 4;
__REG32          :28;
} __vicvectpr_bits;

/* VIC Software Priority register */
typedef struct{
__REG32 SWPRIORITY:16;
__REG32           :16;
} __vicswprmask_bits;

/* VIC protection enable register */
typedef struct{
__REG32 VIC_ACCESS  : 1;
__REG32             :31;
} __vicprotection_bits;

/* Pin function select register 0 */
typedef struct{
__REG32 P0_0   : 2;
__REG32 P0_1   : 2;
__REG32 P0_2   : 2;
__REG32 P0_3   : 2;
__REG32 P0_4   : 2;
__REG32 P0_5   : 2;
__REG32 P0_6   : 2;
__REG32 P0_7   : 2;
__REG32 P0_8   : 2;
__REG32 P0_9   : 2;
__REG32 P0_10  : 2;
__REG32 P0_11  : 2;
__REG32 P0_12  : 2;
__REG32 P0_13  : 2;
__REG32 P0_14  : 2;
__REG32 P0_15  : 2;