📄 bsp.c
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switch (CLKSRCSEL & 0x03) { /* Determine the current clock source. */
case 0:
clk_src = BSP_IRC_OSC_FRQ;
break;
case 1:
clk_src = BSP_MAIN_OSC_FRQ;
break;
case 2:
clk_src = BSP_RTC_OSC_FRQ;
break;
default:
clk_src = BSP_IRC_OSC_FRQ;
break;
}
pll_stat = PLLSTAT;
if ((DEF_BIT_IS_SET(pll_stat, DEF_BIT_24)) && /* If the PLL is currently enabled and connected. */
(DEF_BIT_IS_SET(pll_stat, DEF_BIT_25))) {
pll_msel = (CPU_INT32U)((pll_stat >> 0 ) & 0x3FFF) + 1;
pll_nsel = (CPU_INT32U)((pll_stat >> 16 ) & 0x000F) + 1;
pll_clk_feq = (2 * pll_msel * (clk_src / pll_nsel)); /* Compute the PLL output frequency. */
} else {
pll_clk_feq = (clk_src); /* The PLL is bypassed. */
}
clk_div = (CPU_INT32U)(CCLKCFG & 0xFF) + 1; /* Obtain the CPU core clock divider. */
clk_freq = (CPU_INT32U)(pll_clk_feq / clk_div); /* Compute the ARM Core clock frequency. */
return (clk_freq);
}
/*
*********************************************************************************************************
* BSP_CPU_PclkFreq()
*
* Description : Get the peripheral clock frequency for a specific peripheral.
*
* Argument(s) : pclk The peripheral clock ID, one of BSP_PCLK_xxx defined in bsp.h.
*
* Return(s) : The peripheral's clock in Hz
*
* Caller(s) : Application.
*
* Note(s) : none.
*********************************************************************************************************
*/
CPU_INT32U BSP_CPU_PclkFreq (CPU_INT08U pclk)
{
CPU_INT32U clk_freq;
CPU_INT32U pclk_freq;
CPU_INT32U sel;
clk_freq = BSP_CPU_ClkFreq();
if (pclk > 29) {
return (CPU_INT32U)0;
}
if (pclk < 16) {
sel = (PCLKSEL0 >> (2 * pclk )) & 0x03;
} else {
sel = (PCLKSEL1 >> (2 * (pclk - 16))) & 0x03;
}
if (sel == 0 ){
pclk_freq = clk_freq / 4;
} else if (sel == 1) {
pclk_freq = clk_freq;
} else if (sel == 2) {
pclk_freq = clk_freq / 2;
} else {
if ((pclk == BSP_PCLK_CAN1) || (pclk == BSP_PCLK_CAN1)) {
pclk_freq = clk_freq / 6;
} else {
pclk_freq = clk_freq / 8;
}
}
return (pclk_freq);
}
/*
*********************************************************************************************************
* OS_CPU_ExceptHndlr()
*
* Description : Handle any exceptions.
*
* Argument(s) : except_type ARM exception type:
*
* OS_CPU_ARM_EXCEPT_RESET 0x00
* OS_CPU_ARM_EXCEPT_UNDEF_INSTR 0x01
* OS_CPU_ARM_EXCEPT_SWI 0x02
* OS_CPU_ARM_EXCEPT_PREFETCH_ABORT 0x03
* OS_CPU_ARM_EXCEPT_DATA_ABORT 0x04
* OS_CPU_ARM_EXCEPT_ADDR_ABORT 0x05
* OS_CPU_ARM_EXCEPT_IRQ 0x06
* OS_CPU_ARM_EXCEPT_FIQ 0x07
*
* Return(s) : none.
*
* Caller(s) : OS_CPU_ARM_EXCEPT_HANDLER(), which is declared in os_cpu_a.s.
*
* Note(s) : (1) Only OS_CPU_ARM_EXCEPT_FIQ and OS_CPU_ARM_EXCEPT_IRQ exceptions handler are implemented.
* For the rest of the exception a infinite loop is implemented for debuging pruposes. This behavior
* should be replaced with another beahvior (reboot, etc).
*********************************************************************************************************
*/
void OS_CPU_ExceptHndlr (CPU_INT32U except_type)
{
CPU_FNCT_VOID pfnct;
CPU_INT32U *sp;
switch (except_type) {
case OS_CPU_ARM_EXCEPT_IRQ:
pfnct = (CPU_FNCT_VOID)VICADDRESS; /* Read the interrupt vector from the VIC. */
if (pfnct != (CPU_FNCT_VOID)0) { /* Make sure we don't have a NULL pointer. */
OS_CPU_SR_INT_En(); /* Enable IRQs & FIQs. */
(*pfnct)(); /* Execute the ISR for the interrupting device. */
OS_CPU_SR_INT_Dis(); /* Disable IRQs & FIQs. */
VICADDRESS = 1; /* Acknowlege the VIC interrupt. */
}
break;
case OS_CPU_ARM_EXCEPT_FIQ:
pfnct = (CPU_FNCT_VOID)VICADDRESS; /* Read the interrupt vector from the VIC. */
if (pfnct != (CPU_FNCT_VOID)0) { /* Make sure we don't have a NULL pointer. */
(*pfnct)(); /* Execute the ISR for the interrupting device. */
VICADDRESS = 1; /* Acknowlege the VIC interrupt. */
}
break;
case OS_CPU_ARM_EXCEPT_RESET:
/* $$$$ Insert code to handle a Reset exception */
case OS_CPU_ARM_EXCEPT_UNDEF_INSTR:
/* $$$$ Insert code to handle a Undefine Instruction exception */
case OS_CPU_ARM_EXCEPT_SWI:
/* $$$$ Insert code to handle a Software exception */
case OS_CPU_ARM_EXCEPT_PREFETCH_ABORT:
/* $$$$ Insert code to handle a Prefetch Abort exception */
case OS_CPU_ARM_EXCEPT_DATA_ABORT:
/* $$$$ Insert code to handle a Data Abort exception */
case OS_CPU_ARM_EXCEPT_ADDR_ABORT:
/* $$$$ Insert code to handle a Address Abort exception */
default:
if (OSIntNesting == 1) {
sp = (CPU_INT32U *)OSTCBCur->OSTCBStkPtr;
} else {
sp = (CPU_INT32U *)OS_CPU_ExceptStkPtr;
}
BSP_TRACE_INFO(("\nCPU_ARM_EXCEPTION #%d trapped.\n", except_type));
BSP_TRACE_INFO(("R0 : 0x%08x\n", *(sp + 0x01)));
BSP_TRACE_INFO(("R1 : 0x%08x\n", *(sp + 0x02)));
BSP_TRACE_INFO(("R2 : 0x%08x\n", *(sp + 0x03)));
BSP_TRACE_INFO(("R3 : 0x%08x\n", *(sp + 0x04)));
BSP_TRACE_INFO(("R4 : 0x%08x\n", *(sp + 0x05)));
BSP_TRACE_INFO(("R5 : 0x%08x\n", *(sp + 0x06)));
BSP_TRACE_INFO(("R6 : 0x%08x\n", *(sp + 0x07)));
BSP_TRACE_INFO(("R7 : 0x%08x\n", *(sp + 0x08)));
BSP_TRACE_INFO(("R8 : 0x%08x\n", *(sp + 0x09)));
BSP_TRACE_INFO(("R9 : 0x%08x\n", *(sp + 0x0A)));
BSP_TRACE_INFO(("R10 : 0x%08x\n", *(sp + 0x0B)));
BSP_TRACE_INFO(("R11 : 0x%08x\n", *(sp + 0x0C)));
BSP_TRACE_INFO(("R12 : 0x%08x\n", *(sp + 0x0D)));
BSP_TRACE_INFO(("SP : 0x%08x\n", sp));
BSP_TRACE_INFO(("LR : 0x%08x\n", *(sp + 0x0E)));
BSP_TRACE_INFO(("PC : 0x%08x\n", *(sp + 0x0F)));
BSP_TRACE_INFO(("CPSR: 0x%08x\n", *(sp + 0x00)));
while (DEF_FALSE) { /* Infinite loop on other exceptions. (see note #1) */
;
}
}
}
/*
*********************************************************************************************************
* BSP_IntDisAll()
*
* Description : Disable ALL interrupts.
*
* Argument(s) : none.
*
* Return(s) : none.
*
* Caller(s) : Application
*
* Note(s) : none.
*********************************************************************************************************
*/
void BSP_IntDisAll (void)
{
VICINTENCLEAR = 0xFFFFFFFFL; /* Disable ALL interrupts. */
}
/*
*********************************************************************************************************
* BSP_SDRAM_Init()
*
* Description : Initialize external SDRAM.
* (1) Configure the I/O for the SDRAM.
* (2) Enable the External Memory controller.
* (3) Set the Dynamics/Statics parameters.
* (4) Initializes the SDRAM.
*
* Argument(s) : none.
*
* Return(s) : DEF_FALSE If the SDRAM could not be initialized.
*
* DEF_TRUE if the SDRAM was initialized without errors
*
* Caller(s) : Application.
*
* Note(s) : none.
*********************************************************************************************************
*/
CPU_BOOLEAN BSP_SDRAM_Init (void)
{
CPU_INT32U i;
CPU_INT32U dummy;
CPU_INT32U cpu_clk;
CPU_INT32U reg_val;
CPU_FP32 sdram_per;
/* ---------------- I/O CONFIGURATION --------------------- */
PINSEL5 &= (0xF0FCFCC0);
PINSEL5 |= (0x05010115);
PINMODE5 &= (0xF0FCFCC0);
PINMODE5 |= (0x0A02022A);
PINSEL6 = (0x55555555);
PINMODE6 = (0xAAAAAAAA);
PINSEL8 &= (0xC0000000);
PINSEL8 |= (0x15555555);
PINMODE8 &= (0xC0000000);
PINMODE8 |= (0x2AAAAAAA);
PINSEL9 &= (0xFFF3FFFF);
PINSEL9 |= (0x00040000);
PINMODE9 &= (0xFFF3FFFF);
PINMODE9 |= (0x00080000);
/* ----------- (2) INITIALIZE SDRAM CONTROLLER ------------- */
PCONP |= DEF_BIT_11; /* Enable PCEMC in the Power control register */
EMCCONTROL = DEF_BIT_00; /* Enable EMC */
EMCDINAMICRDCFG = 1;
EMCDYNAMICRASCAS0 = (0x03 << 0) /* RAS Latency = CAS Latency = 0x3 = Three CCLK Cycles */
| (0x03 << 8);
cpu_clk = BSP_CPU_ClkFreq();
for (i = 0; i < 5; i++) {
if (cpu_clk = BSP_CPU_FreqTbl[i]) {
sdram_per = BSP_SDRAM_PerTbl[i];
i = 100;
} else if (cpu_clk < BSP_CPU_FreqTbl[i]) {
return DEF_FALSE;
}
}
EMCDYNAMICRP = BSP_PER_TO_CLK(sdram_per, BSP_SDRAM_TRP);
EMCDYNAMICRAS = BSP_PER_TO_CLK(sdram_per, BSP_SDRAM_TRAS);
EMCDYNAMICSREX = BSP_PER_TO_CLK(sdram_per, BSP_SDRAM_TXSR);
EMCDYNAMICAPR = BSP_SDRAM_TAPR;
EMCDYNAMICDAL = BSP_SDRAM_TDAL + BSP_PER_TO_CLK(sdram_per, BSP_SDRAM_TRP);
EMCDYNAMICWR = BSP_SDRAM_TWR;
EMCDYNAMICRC = BSP_PER_TO_CLK(sdram_per, BSP_SDRAM_TRC);
EMCDYNAMICRFC = BSP_PER_TO_CLK(sdram_per, BSP_SDRAM_TRFC);
EMCDYNAMICXSR = BSP_PER_TO_CLK(sdram_per, BSP_SDRAM_TXSR);
EMCDYNAMICRRD = BSP_PER_TO_CLK(sdram_per, BSP_SDRAM_TRRD);
EMCDYNAMICMRD = BSP_SDRAM_TMRD;
EMCDYNAMICCFG0 = 0x0000680; /* 13 row, 9 - col, SDRAM */
/* JEDEC General SDRAM Initialization Sequence */
/* DELAY to allow power and clocks to stabilize ~100 us */
/* NOP */
EMCDINAMICCTRL = 0x0183;
OSTimeDlyHMSM(0, 0, 0, 1);
reg_val = EMCDINAMICCTRL;
reg_val &= ~BSP_EMC_DYNAMIC_CTRL_INIT_MASK;
reg_val |= BSP_EMC_DYNAMIC_CTRL_INIT_PALL;
EMCDINAMICCTRL = reg_val; /* SDRAM PALL Command */
EMCDINAMICRFR = 1;
OSTimeDlyHMSM(0, 0, 0, 1);
EMCDINAMICRFR = (BSP_PER_TO_CLK(sdram_per, BSP_SDRAM_REFRESH) >> 4);
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