📄 atp.c
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return (440*3+Mod_re_len); } return 0; }}static int write_test(struct file *file, const char *buf, size_t count, loff_t *loff_t){ if(count <= 900) //the length of data that from Lan is less 460 { for(;((mod_to_bus_flag == 1) && (Bus_wr_in == Mod_wr_in));); /* if((mod_to_bus_flag == 1) & (Bus_wr_in == Mod_wr_in)) { Bus_wr_in++; if(Bus_wr_in == Num_buf) { Bus_wr_in = 0; mod_to_bus_flag = 0; } }*/ memcpy(&Mod_to_Bus[Mod_wr_in][16], buf, count); Mod_to_Bus[Mod_wr_in][6] = 0x1; Mod_to_Bus[Mod_wr_in][7] = (count >> 8); Mod_to_Bus[Mod_wr_in][8] = (0x0ff & count); Mod_to_Bus[Mod_wr_in][9] = 0x0; Mod_wr_in++; if(Mod_wr_in == Num_buf) { mod_to_bus_flag = 1; Mod_wr_in = 0; } } else { for(;((mod_to_bus_flag == 1) && (Bus_wr_in == Mod_wr_in)););/* if((mod_to_bus_flag == 1) & (Bus_wr_in == Mod_wr_in)) { Bus_wr_in++; if(Bus_wr_in == Num_buf) { Bus_wr_in = 0; mod_to_bus_flag = 0; } }*/ memcpy(&Mod_to_Bus[Mod_wr_in][16], buf, 900); Mod_to_Bus[Mod_wr_in][6] = 0x2; Mod_to_Bus[Mod_wr_in][7] = 0x3; Mod_to_Bus[Mod_wr_in][8] = 0x84; Mod_to_Bus[Mod_wr_in][9] = 0x1;// for(ttp = 0; ttp < 920; ttp++)// {// printk("%d ", Mod_to_Bus[Mod_wr_in][ttp]); // } Mod_wr_in++; if(Mod_wr_in == Num_buf) { Mod_wr_in = 0; mod_to_bus_flag = 1; } //************** for(;((mod_to_bus_flag == 1) && (Bus_wr_in == Mod_wr_in)););/* if((mod_to_bus_flag == 1) & (Bus_wr_in == Mod_wr_in)) { Bus_wr_in++; if(Bus_wr_in == Num_buf) { Bus_wr_in = 0; mod_to_bus_flag = 0; } }*/ memcpy(&Mod_to_Bus[Mod_wr_in][16],(buf+900),(count-900)); Mod_to_Bus[Mod_wr_in][6] = 0x2; Mod_to_Bus[Mod_wr_in][7] = (count-900)>>8; Mod_to_Bus[Mod_wr_in][8] = (0x0ff & (count-900)); Mod_to_Bus[Mod_wr_in][9] = 0x2; Mod_wr_in++; if(Mod_wr_in == Num_buf) { mod_to_bus_flag = 1; Mod_wr_in = 0; } } return count;}static int open_test(struct inode *inode, struct file *file){ MOD_INC_USE_COUNT; return 0;}static void release_test(struct inode *inode, struct file *file){ MOD_DEC_USE_COUNT;}struct file_operations test_fops = { read:read_test, write:write_test, open:open_test, release:(void(*))release_test,};//***********************************void irq_handler(int irq, void *dev_id, struct pt_regs *regs){/* addt++; for(ttp = 0; ttp < 920; ttp++) { xx[ttp]=yy; } yy++; copy_to_user(addr_Wr, &xx[0], 920);// printk("inter the irp2 \n");*///******************begin the bus write if((Bus_wr_in == Mod_wr_in) & (mod_to_bus_flag == 0)) { memcpy(addr_Wr, &SendNull[0], (Len_Wr_bus));//write the null data to bus// for(ttp = 0; ttp < 4; ttp++)// { *(addr_Wr+920/4) = 0x0;// } } else { memcpy(addr_Wr, &Mod_to_Bus[Bus_wr_in][0], (Len_Wr_bus));// for(ttp = 0; ttp < 4; ttp++)// { *(addr_Wr+920/4) = 0x0;// }// printk("%d , %d , %d ,%d \n", ((char*)addr_Wr)[4], ((char*)addr_Wr)[5], ((char*)addr_Wr)[6], ((char*)addr_Wr)[9]); Bus_wr_in++; if(Bus_wr_in == Num_buf) { Bus_wr_in = 0; mod_to_bus_flag = 0; }// printk("write a real data! \n"); }// printk("9th = %d \n", Mod_to_Bus[Bus_wr_in-1][9]);//end the bus write//*********************************//begin the bus read memcpy(&Bus_to_Mod[Bus_re_in][0], addr_Re, Len_Re_bus); if((Bus_to_Mod[Bus_re_in][4] == 0x77) & (Bus_to_Mod[Bus_re_in][5] == 0xff) & (Bus_to_Mod[Bus_re_in][456] == 0x47) & (Bus_to_Mod[Bus_re_in][457] == 0x48) & (Bus_to_Mod[Bus_re_in][458] == 0x0ff) & (Bus_to_Mod[Bus_re_in][459] == 0x7d)) { if(Bus_to_Mod[Bus_re_in][6] != 0) {// printk("'"); if((bus_to_mod_flag == 1) && (Bus_re_in == Mod_re_in)) { Mod_re_in++; if(Mod_re_in == Num_buf) { Mod_re_in = 0; bus_to_mod_flag = 0; } } Bus_re_in++; if(Bus_re_in == Num_buf) { Bus_re_in = 0; bus_to_mod_flag = 1; } } }}//***********************************int init_module(void){ int result; int check_i; init_mem();//****************************registe the char device result = register_chrdev(0, "test", &test_fops); if (result <0) { printk("test:can't get major number \n"); return result; } if (test_major == 0) test_major = result; printk("\n"); printk("***************************\n"); printk("the test_major = %d \n", test_major); printk("the module have been register from the kernel!\n"); printk("***************************\n");//*****************************check the region for write the extern memory check_i = check_region(Base_addr_wr, Len_Wr); if(check_i != 0) { printk("this region cann't be used!\n"); return(0); } printk("check write region ok!\n"); request_region(Base_addr_wr, Len_Wr, "test"); //**************************** init_timer(&mytimer); mytimer.expires = jiffies +1*HZ; mytimer.function = myfun; mytimer.data = 2234;// add_timer(&mytimer);//*****************************check the region for read the extern memory check_i = check_region(Base_addr_re, Len_Re); if(check_i != 0) { printk("this region cann't be used!\n"); return(0); } printk("check read region ok!\n"); request_region(Base_addr_re, Len_Re, "test");////////////////////////////////memory ioremap to the phy address and config the operation mode:w addr_Wr = ioremap(Base_addr_wr, Len_Wr); addr_Re = ioremap(Base_addr_re, Len_Re);//////////////////// Ext_r_GPFCON = (unsigned int *)ioremap(irq_addr,irq_len); printk("%x\n",Ext_r_GPFCON); *Ext_r_GPFCON = irq_mod;////////////////// Ext_r_GPFCON = (unsigned int *)ioremap(0xffffff78, irq_len); *Ext_r_GPFCON=0x00004088; ////////////////////////////////////////////interrupt requestprintk("***Bigen request the IRQ ***\n");result = request_irq( IRQ_EXTIRQ, irq_handler, SA_INTERRUPT, "irq0_first", NULL);// (void *) irq_handler); if(result == 0) printk("The interrupt is sucessful!\n"); enable_irq(IRQ_EXTIRQ); return 0;}void cleanup_module(void){ unregister_chrdev(test_major, "test"); printk("***************************\n"); printk("Have released the module from the kernel! \n"); printk("***************************\n"); printk("release the region....\n"); release_region(Base_addr_wr,Len_Wr); release_region(Base_addr_re,Len_Re); printk(".... ok!\n"); del_timer(&mytimer);//********delete the interrupt printk("release the interrupt.....\n"); disable_irq(IRQ_EXTIRQ); free_irq(IRQ_EXTIRQ, NULL); printk("....ok!\n");}/*switch(Read_Bus[6]) { int leng_d; case 0: ;break; case 1: if((Read_Bus[436] == 0x47)& (Read_Bus[437] == 0x47)& (Read_Bus[438] == 0xff)&( Read_Bus[439] == 0x7d)) //check the last 4 data , the data read include one pack lan data { leng_d = Read_Bus[7]; leng_d<<8; leng_d = leng_d||Read_Bus[8]; memcpy(&Read_mod[mod_wr_in], &Read_Bus[16], leng_d); mod_wr_in++; if(mod_wr_in == 10) { mod_wr_in == 0; mod_lan_full = 1; } } break; case 2: if((Read_Bus[436] == 0x47)& (Read_Bus[437] == 0x47)& (Read_Bus[438] == 0xff)&( Read_Bus[439] == 0x7d)) //check the last 4 data , the data read partition to 2 { if(dis_pack_in == 0) { memcpy(&dis_pack_buff[0], &Read_Bus[16], Len_Re_bus); dis_pack_in = 1; } } else { leng_d = 0x0; leng_d = Read_Bus[7]; leng_d<<8; leng_d = leng_d||Read_Bus[8]; memcpy(&dis_pack_buff[440], &Read_Bus[16], leng_d); memcpy(&Read_mod[mod_wr_in][0], &dis_pack_buff[0], (440+leng_d)); mod_wr_in++; if(mod_wr_in == 10) { mod_wr_in = 0; mod_lan_full = 1; dis_pack_in = 0; } } break;// case: }*/
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