📄 hostctrl.c
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/*************************************************************************/
/* */
/* The last modification date: 02-23-2004 */
/* REMARKS: Created initial version 1.0 */
/* */
/* Copyright (C) 2004 Vimicro CO.,LTD */
/*************************************************************************/
#include "v558def.h"
#include "vregdef.h"
#include "high_api.h"
#include "v558api.h"
extern US558_VIDEO_STATUS VideoFrame;
extern UINT8 g_558_WorkStatus;
//****************************************************************************************
//Provide the functions in the vrdk.raf.
//****************************************************************************************
void DrvSetMultiSel(VMV_MULTI_SEL sel); //Set register 188c ,(multi8)
#define NOINT 0xc0
UINT16 g_V558HoldClk = 1;
UINT8 g_V558DelayFactor = 1;
UINT16 g_V558HoldClkChg = 1;
//#define MEM_HOLDCLK() {if(g_V558HoldClk) {g_V558HoldClkChg = g_V558HoldClk; while(g_V558HoldClkChg--);} }
#define MEM_HOLDCLK() //{for(g_V558HoldClk=0;g_V558HoldClk++;g_V558HoldClk<1); }
#define JBUF_DELAY 200
#define OS_ENTER_CRITICAL() //IRQFIQDE /* Disable interrupts */
/* Note: R0 register need not be saved, for it gets saved outside. Refer SDT userguide 6-5 */
//#define IRQFIQDE __asm
//{ \
// mrs r0,CPSR; \
// stmfd sp!,{r0}; \
// orr r0,r0,#NOINT; \
// msr CPSR_c,r0; \
//}
#define OS_EXIT_CRITICAL() //IRQFIQRE /* Restore interrupts */
//#define IRQFIQRE __asm
//{ \
// ldmfd sp!,{r0}; \
// msr CPSR_c,r0; \
//}
//zlj 4.21 modify start----------
#if 1
extern void Delay(int time);
void V558_Delay(UINT32 time)
{
//time*=10; // angela
if(time)
{
Delay(time*g_V558DelayFactor);
}
}
#else
//extern void delayus(UINT32 value);
void V558_Delay(UINT32 time)
{
//time*=10; // angela
if(time)
{
//delayus(400*time*g_V558DelayFactor); //2005.4.21 19:26
delayus(400*time*g_V558DelayFactor); //2005.4.21 19:26
}
}
#endif
//zlj 4.21 modify end-------------
#if V558_BUS_TYPE == V558_BUS_SEPERATE
#if 0 //2005.5.5 mask
void V558_GetReg(UINT32 uAddr, UINT8 *uVal)
{
if(uAddr < 0x10000)
{
OS_ENTER_CRITICAL()
*(volatile UINT8 *)(HOST_ADDR_REGUIA) = (UINT8)((uAddr&0xff00)>>8);
MEM_HOLDCLK()
*uVal = *(volatile UINT8 *)((UINT32)INTER_ADDR_REGUIA + (UINT32)(uAddr&0xff));
MEM_HOLDCLK()
OS_EXIT_CRITICAL()
}
else //sram debug
{
if((uAddr >= 0x20000) && (uAddr < 0x30000)) //Jbuf
{
//reg V558_REG_BIU_SEL_PORT = 0, not select port access (only effect Jbuf sram)
V558_SetReg((UINT16)V558_REG_BIU_SEL_PORT,0);
}
OS_ENTER_CRITICAL()
*(volatile UINT8 *)(HOST_ADDR_REGUIA) = (UINT8)((uAddr&0xff00)>>8);
MEM_HOLDCLK()
*uVal = *(volatile UINT8 *)((UINT32)INTER_ADDR_REGUIA + (UINT32)(uAddr&0xff)+(UINT32)((uAddr>>8)&0x300));
MEM_HOLDCLK()
OS_EXIT_CRITICAL()
if((uAddr >= 0x20000) && (uAddr < 0x30000)) //Jbuf
V558_SetReg((UINT16)V558_REG_BIU_SEL_PORT,1);
}
}
void V558_SetReg(UINT32 uAddr, UINT8 uVal)
{
if(uAddr < 0x10000)
{
OS_ENTER_CRITICAL()
*(volatile UINT8 *)(HOST_ADDR_REGUIA) = (UINT8)((uAddr&0xff00)>>8);
MEM_HOLDCLK()
*(volatile UINT8 *)((UINT32)INTER_ADDR_REGUIA + (UINT32)(uAddr&0xff)) = (UINT8)(uVal&0xff);
MEM_HOLDCLK()
OS_EXIT_CRITICAL()
}
else //sram debug
{
if((uAddr >= 0x20000) && (uAddr < 0x30000)) //Jbuf
{
//reg V558_REG_BIU_SEL_PORT = 0, not select port access (only effect Jbuf sram)
V558_SetReg((UINT16)V558_REG_BIU_SEL_PORT,0);
}
OS_ENTER_CRITICAL()
*(volatile UINT8 *)(HOST_ADDR_REGUIA) = (UINT8)((uAddr&0xff00)>>8);
MEM_HOLDCLK()
*(volatile UINT8 *)((UINT32)INTER_ADDR_REGUIA + (UINT32)(uAddr&0xff) +(UINT32)((uAddr>>8)&0x300)) = (UINT8)(uVal&0xff);
MEM_HOLDCLK()
OS_EXIT_CRITICAL()
if((uAddr >= 0x20000) && (uAddr < 0x30000)) //Jbuf
V558_SetReg((UINT16)V558_REG_BIU_SEL_PORT,1);
}
}
void V558_ReadSram(UINT32 uStartAddr, UINT8* pData, UINT32 uSize)
{
V558_SetReg((UINT16)V558_REG_BIU_SEL_PORT,0x1);
OS_ENTER_CRITICAL()
*(volatile UINT8 *)(HOST_ADDR_MEMUIA) = (UINT8)((uStartAddr>>10)&0xff);
MEM_HOLDCLK()
*(volatile UINT8 *)(HOST_ADDR_MEMLIA) = (UINT8)((uStartAddr>>2)&0xff);
MEM_HOLDCLK()
*(volatile UINT8 *)(HOST_ADDR_MEMLIA0) = (UINT8)(uStartAddr&0x3);
MEM_HOLDCLK()
if((uStartAddr>=0x20000) && (uStartAddr<0x30000))//Jpeg buffer
{
while(uSize--)
{
*(pData++) = *(volatile UINT8 *)(HOST_ADDR_MEMPORT);
MEM_HOLDCLK()
}
}
else
{
while(uSize--)
{
*(pData++) = *(volatile UINT8 *)(HOST_ADDR_MEMDATA);
MEM_HOLDCLK()
}
}
OS_EXIT_CRITICAL()
}
void V558_WriteLcdSram(UINT32 uStartAddr, UINT16* pData, UINT32 uSize)
{
UINT8 uTemp = 0;
V558_SetReg((UINT16)V558_REG_BIU_SEL_PORT,0x1);
OS_ENTER_CRITICAL()
*(volatile UINT8 *)(HOST_ADDR_MEMUIA) = (UINT8)((uStartAddr>>10)&0xff);
MEM_HOLDCLK()
*(volatile UINT8 *)(HOST_ADDR_MEMLIA) = (UINT8)((uStartAddr>>2)&0xff);
MEM_HOLDCLK()
*(volatile UINT8 *)(HOST_ADDR_MEMLIA0) = (UINT8)(uStartAddr&0x3);
MEM_HOLDCLK()
while(uSize>0)
{
uTemp =(UINT8)(*(pData)>>8);
*(volatile UINT8 *)(HOST_ADDR_MEMPORT) = uTemp;
MEM_HOLDCLK();
uTemp =(UINT8)(*(pData));
*(volatile UINT8 *)(HOST_ADDR_MEMPORT) = uTemp;
MEM_HOLDCLK()
pData++;
uSize--;
}
OS_EXIT_CRITICAL();
}
void V558_WriteSram(UINT32 uStartAddr, UINT8* pData, UINT32 uSize)
{
UINT8 *p = pData+uSize;
V558_SetReg((UINT16)V558_REG_BIU_SEL_PORT,0x1);
OS_ENTER_CRITICAL()
*(volatile UINT8 *)(HOST_ADDR_MEMUIA) = (UINT8)((uStartAddr>>10)&0xff);
MEM_HOLDCLK()
*(volatile UINT8 *)(HOST_ADDR_MEMLIA) = (UINT8)((uStartAddr>>2)&0xff);
MEM_HOLDCLK()
*(volatile UINT8 *)(HOST_ADDR_MEMLIA0) = (UINT8)(uStartAddr&0x3);
MEM_HOLDCLK()
if((uStartAddr>=0x20000) && (uStartAddr<0x30000))//Jpeg buffer
{
while(pData < p)
{
*(volatile UINT8 *)(HOST_ADDR_MEMPORT) = *(pData++);
MEM_HOLDCLK()
}
}
else
{
while(pData < p)
{
*(volatile UINT8 *)(HOST_ADDR_MEMPORT) = *(pData++);
MEM_HOLDCLK()
}
}
OS_EXIT_CRITICAL()
}
#endif
#endif
#if V558_BUS_TYPE == V558_BUS_MULTI8
void V558_GetReg(UINT32 uAddr, UINT8 *uVal)
{
if(uAddr < 0x8000)
{
OS_ENTER_CRITICAL()
// GPIO_WriteIO(0,19);
*(volatile UINT8 *)(MULTI8_ADDR_CTRL) = (UINT8)MULTI8_REG_WORDH;
MEM_HOLDCLK()
// GPIO_WriteIO(1,19);
*(volatile UINT8 *)(MULTI8_ADDR_DATA) = (UINT8)((uAddr&0xff00)>>8);
MEM_HOLDCLK()
// GPIO_WriteIO(0,19);
*(volatile UINT8 *)(MULTI8_ADDR_CTRL) = (UINT8)MULTI8_REG_WORDL;
MEM_HOLDCLK()
// GPIO_WriteIO(1,19);
*(volatile UINT8 *)(MULTI8_ADDR_DATA) = (UINT8)(uAddr&0xff);
MEM_HOLDCLK()
// GPIO_WriteIO(0,19);
*(volatile UINT8 *)(MULTI8_ADDR_CTRL) = (UINT8)MULTI8_REG_PORT;
MEM_HOLDCLK()
// GPIO_WriteIO(1,19);
*uVal = *(volatile UINT8 *)(MULTI8_ADDR_DATA);
MEM_HOLDCLK()
OS_EXIT_CRITICAL()
}
else //sram debug
{
if((uAddr >= 0x20000) && (uAddr < 0x30000))//Jpeg buffer
{
//reg V558_REG_BIU_SEL_PORT = 0, not select port access (only effect Jbuf sram)
V558_SetReg((UINT16)V558_REG_BIU_SEL_PORT,0x0);
}
V558_SetReg((UINT16)V558_REG_BIU_INCREMENT,0x0); //Addr not auto increate(only effect sram)
V558_SetReg((UINT16)V558_REG_BIU_MEM_HIGH_WORD,(UINT8)((uAddr&0x30000)>>16));
V558_SetReg((UINT16)V558_REG_BIU_MEM_LOW_WORD_H,(UINT8)((uAddr&0xff00)>>8));
V558_SetReg((UINT16)V558_REG_BIU_MEM_LOW_WORD_L,(UINT8)(uAddr&0xff));
OS_ENTER_CRITICAL()
//Set multi8 emory port addr
// GPIO_WriteIO(0,19);
*(volatile UINT8 *)(MULTI8_ADDR_CTRL) = MULTI8_MEM_PORT;
MEM_HOLDCLK()
// GPIO_WriteIO(1,19);
*uVal = *(volatile UINT8 *)(MULTI8_ADDR_DATA);
MEM_HOLDCLK()
OS_EXIT_CRITICAL()
if((uAddr >= 0x20000) && (uAddr < 0x30000)) //Jbuf
V558_SetReg((UINT16)V558_REG_BIU_SEL_PORT,1);
// GPIO_WriteIO(0,19);
}
}
void V558_SetReg(UINT32 uAddr, UINT8 uVal)
{
if(uAddr < 0x8000)
{
OS_ENTER_CRITICAL()
// GPIO_WriteIO(0,19);
*(volatile UINT8 *)(MULTI8_ADDR_CTRL) = (UINT8)MULTI8_REG_WORDH;
MEM_HOLDCLK()
// GPIO_WriteIO(1,19);
*(volatile UINT8 *)(MULTI8_ADDR_DATA) = (UINT8)((uAddr&0xff00)>>8);
MEM_HOLDCLK()
// GPIO_WriteIO(0,19);
*(volatile UINT8 *)(MULTI8_ADDR_CTRL) = (UINT8)MULTI8_REG_WORDL;
MEM_HOLDCLK()
// GPIO_WriteIO(1,19);
*(volatile UINT8 *)(MULTI8_ADDR_DATA) = (UINT8)(uAddr&0xff);
MEM_HOLDCLK()
// GPIO_WriteIO(0,19);
*(volatile UINT8 *)(MULTI8_ADDR_CTRL) = (UINT8)MULTI8_REG_PORT;
MEM_HOLDCLK()
// GPIO_WriteIO(1,19);
*(volatile UINT8 *)(MULTI8_ADDR_DATA) = uVal;
MEM_HOLDCLK()
OS_EXIT_CRITICAL()
}
else //sram debug
{
if((uAddr >= 0x20000) && (uAddr < 0x30000))//Jpeg buffer
{
//reg V558_REG_BIU_SEL_PORT = 0, not select port access (only effect Jbuf sram)
V558_SetReg(V558_REG_BIU_SEL_PORT,0x0);
}
V558_SetReg((UINT16)V558_REG_BIU_INCREMENT,0x0); //Addr not auto increate(only effect sram)
V558_SetReg((UINT16)V558_REG_BIU_MEM_HIGH_WORD,(UINT8)((uAddr&0x30000)>>16));
V558_SetReg((UINT16)V558_REG_BIU_MEM_LOW_WORD_H,(UINT8)((uAddr&0xff00)>>8));
V558_SetReg((UINT16)V558_REG_BIU_MEM_LOW_WORD_L,(UINT8)(uAddr&0xff));
OS_ENTER_CRITICAL()
//Set multi8 emory port addr
// GPIO_WriteIO(0,19);
*(volatile UINT8 *)(MULTI8_ADDR_CTRL) = MULTI8_MEM_PORT;
MEM_HOLDCLK()
// GPIO_WriteIO(1,19);
*(volatile UINT8 *)(MULTI8_ADDR_DATA) = uVal;
MEM_HOLDCLK()
OS_EXIT_CRITICAL()
if((uAddr >= 0x20000) && (uAddr < 0x30000)) //Jbuf
V558_SetReg((UINT16)V558_REG_BIU_SEL_PORT,1);
// GPIO_WriteIO(0,19);
}
}
void V558_ReadSram(UINT32 uStartAddr, UINT8* pData, UINT32 uSize)
{
if((uStartAddr>=0x08000) && (uStartAddr<0x20000))//Lcd 40k buffer or lbuf
{
V558_SetReg(V558_REG_BIU_MUL_CLR_AUTO, 0x1);
}
V558_SetReg((UINT16)V558_REG_BIU_SEL_PORT,0x1);
V558_SetReg((UINT16)V558_REG_BIU_INCREMENT,0x1); //Addr auto increate(only effect sram)
V558_SetReg((UINT16)V558_REG_BIU_MEM_LOW_WORD_H, (UINT8)((uStartAddr&0xff00)>>8));
V558_SetReg((UINT16)V558_REG_BIU_MEM_LOW_WORD_L, (UINT8)(uStartAddr&0xff));
V558_SetReg((UINT16)V558_REG_BIU_MEM_HIGH_WORD, (UINT8)((uStartAddr&0x30000)>>16));
OS_ENTER_CRITICAL()
//Set multi8 emory port addr
// GPIO_WriteIO(0,19);
*(volatile UINT8 *)(MULTI8_ADDR_CTRL) = MULTI8_MEM_PORT;
MEM_HOLDCLK()
while(uSize>0)
{
// GPIO_WriteIO(1,19);
*pData = *(volatile UINT8 *)(MULTI8_ADDR_DATA);
MEM_HOLDCLK()
pData++;
uSize--;
}
OS_EXIT_CRITICAL()
if((uStartAddr>=0x08000) && (uStartAddr<0x20000))//Lcd 40k buffer or lbuf
{
V558_SetReg(V558_REG_BIU_MUL_CLR_AUTO, 0x0);
}
// GPIO_WriteIO(0,19);
}
void V558_WriteLcdSram(UINT32 uStartAddr, UINT16* pData, UINT32 uSize)
{
UINT8 uTemp = 0;
if((uStartAddr>=0x08000) && (uStartAddr<0x20000))//Lcd 40k buffer or lbuf
{
V558_SetReg(V558_REG_BIU_MUL_CLR_AUTO, 0x1);
}
V558_SetReg((UINT16)V558_REG_BIU_SEL_PORT,0x1);
V558_SetReg((UINT16)V558_REG_BIU_INCREMENT,0x1); //Addr auto increate(only effect sram)
V558_SetReg((UINT16)V558_REG_BIU_MEM_LOW_WORD_H,(UINT8)((uStartAddr&0xff00)>>8));
V558_SetReg((UINT16)V558_REG_BIU_MEM_LOW_WORD_L,(UINT8)(uStartAddr&0xff));
V558_SetReg((UINT16)V558_REG_BIU_MEM_HIGH_WORD,(UINT8)((uStartAddr&0x30000)>>16));
OS_ENTER_CRITICAL()
// GPIO_WriteIO(0,19);
*(volatile UINT8 *)(MULTI8_ADDR_CTRL) = MULTI8_MEM_PORT;
while(uSize>0)
{
uTemp =(UINT8)(*(pData)>>8);
// GPIO_WriteIO(1,19);
*(volatile UINT8*)(MULTI8_ADDR_DATA) = uTemp;
MEM_HOLDCLK();
uTemp =(UINT8)(*(pData));
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