reset-02.04.dis

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./reset-02.04.elf:     file format elf32-bigmips

Disassembly of section .text:

9fc00000 <__reset_vector>:
	/*  Address 0xBfc00010 is reserved for boardID on boards
	 *  from MIPS Technologies, so branch to 0xBfc00018 (registers
	 *  on CBUS are 64 bit aligned).
	 */
	b	1f      /* 0xBfc00000 */
9fc00000:	10000005 	b	9fc00018 <_ftext+0x18>
	nop		/* 0xBfc00004 */
9fc00004:	00000000 	nop
	...
	nop		/* 0xBfc00008 */
	nop		/* 0xBfc0000C */
9fc00010:	ffffffff 	sdc3	$31,-1($ra)
9fc00014:	ffffffff 	sdc3	$31,-1($ra)
	.word 0xffffffff/* 0xBfc00010 - illegal board if not intercepted */
	.word 0xffffffff/* 0xBfc00014 -               expanded to 64 bit */
1:					
	/* Clear watch registers */
	MTC0(	zero, C0_WatchLo)
9fc00018:	00000000 	nop
9fc0001c:	40809000 	mtc0	$zero,$watchlo
9fc00020:	00000040 	ssnop
9fc00024:	00000040 	ssnop
9fc00028:	00000040 	ssnop
9fc0002c:	00000040 	ssnop
	MTC0(	zero, C0_WatchHi)
9fc00030:	00000000 	nop
9fc00034:	40809800 	mtc0	$zero,$watchhi
9fc00038:	00000040 	ssnop
9fc0003c:	00000040 	ssnop
9fc00040:	00000040 	ssnop
9fc00044:	00000040 	ssnop

	/* Disable interrupts and KSU field (power up issue) */
	MFC0(   k0, C0_Status)
9fc00048:	401a6000 	mfc0	$k0,$status
	li	k1, ~(M_StatusIE | M_StatusKSU)
9fc0004c:	241bffe6 	li	$k1,-26
	and	k0, k1
9fc00050:	035bd024 	and	$k0,$k0,$k1
	MTC0(	k0, C0_Status)
9fc00054:	00000000 	nop
9fc00058:	409a6000 	mtc0	$k0,$status
9fc0005c:	00000040 	ssnop
9fc00060:	00000040 	ssnop
9fc00064:	00000040 	ssnop
9fc00068:	00000040 	ssnop

	/* Determine endianness */
	li	k1, KSEG1BASE
9fc0006c:	3c1ba000 	lui	$k1,0xa000
	la	k0, digit
9fc00070:	3c1a9fc0 	lui	$k0,0x9fc0
9fc00074:	275a00b4 	addiu	$k0,$k0,180
	or	k0, k1
9fc00078:	035bd025 	or	$k0,$k0,$k1
	lb	k0, 0(k0)
9fc0007c:	835a0000 	lb	$k0,0($k0)
	xor	k0, 0x78
9fc00080:	3b5a0078 	xori	$k0,$k0,0x78
	beq	k0, zero, little_endian
9fc00084:	13400006 	beqz	$k0,9fc000a0 <little_endian>
	nop
9fc00088:	00000000 	nop
	la	k0, _reset_handler_be   /* Defined in linker script */
9fc0008c:	3c1abfc8 	lui	$k0,0xbfc8
9fc00090:	275a8000 	addiu	$k0,$k0,-32768
	or	k0, k1			/* Make sure it is uncached */
9fc00094:	035bd025 	or	$k0,$k0,$k1
	jr	k0
9fc00098:	03400008 	jr	$k0
	nop
9fc0009c:	00000000 	nop

9fc000a0 <little_endian>:

little_endian:	
	la	k0, _reset_handler_le   /* Defined in linker script */
9fc000a0:	3c1abfc1 	lui	$k0,0xbfc1
9fc000a4:	275a0000 	addiu	$k0,$k0,0
	or	k0, k1			/* Make sure it is uncached */
9fc000a8:	035bd025 	or	$k0,$k0,$k1
	jr	k0
9fc000ac:	03400008 	jr	$k0
	nop
9fc000b0:	00000000 	nop

9fc000b4 <digit>:
9fc000b4:	12345678 	beq	$s1,$s4,9fc15a98 <_ecode+0x15540>

9fc000b8 <cacheerr>:

digit:	/* Used for determining endianness */
	.word 0x12345678


	/*
	 * Display "CacheErr" and stay in endless loop.
	 *   contains no endianess dependencies
	 */
cacheerr:
	/* Set k0 = Product ID (determined using REVISION register) */
	li	k0, HIKSEG1(MIPS_REVISION)
9fc000b8:	3c1abfc0 	lui	$k0,0xbfc0
	lw	k0, LO_OFFS(MIPS_REVISION)(k0)
9fc000bc:	8f5a0010 	lw	$k0,16($k0)
	srl	k0, MIPS_REVISION_PROID_SHF
9fc000c0:	001ad102 	srl	$k0,$k0,0x4
	andi	k0, MIPS_REVISION_PROID_MSK >> MIPS_REVISION_PROID_SHF
9fc000c4:	335a000f 	andi	$k0,$k0,0xf

	li      k1, LO_OFFS(ATLAS_ASCIIPOS0)
9fc000c8:	241b0418 	li	$k1,1048
	xori	k0, PRODUCT_ATLASA_ID
9fc000cc:	3b5a0000 	xori	$k0,$k0,0x0
	beq	k0, zero, disp_cacheerr
9fc000d0:	13400013 	beqz	$k0,9fc00120 <disp_cacheerr>
	xori	k0, PRODUCT_MALTA_ID ^ PRODUCT_ATLASA_ID
9fc000d4:	3b5a0002 	xori	$k0,$k0,0x2
	beq	k0, zero, disp_cacheerr
9fc000d8:	13400011 	beqz	$k0,9fc00120 <disp_cacheerr>
	xori	k0, PRODUCT_SEAD_ID ^ PRODUCT_MALTA_ID
9fc000dc:	3b5a0003 	xori	$k0,$k0,0x3

	li	k1, LO_OFFS(SEAD_ASCIIPOS0)
9fc000e0:	241b05c0 	li	$k1,1472
	beq	k0, zero, disp_val_sead
9fc000e4:	13400004 	beqz	$k0,9fc000f8 <disp_val_sead>
	xori	k0, PRODUCT_SEAD2_ID ^ PRODUCT_SEAD_ID
9fc000e8:	3b5a0002 	xori	$k0,$k0,0x2
1:	bne	k0, zero, 1b	/* Unknown platform, so stay here */
9fc000ec:	00000000 	nop
9fc000f0:	1740fffe 	bnez	$k0,9fc000ec <cacheerr+0x34>
	nop
9fc000f4:	00000000 	nop

9fc000f8 <disp_val_sead>:

disp_val_sead:

	/* We support only Basic RTL and MSC01 */
	li	k0, HIKSEG1(SEAD_REVISION)
9fc000f8:	3c1abfc0 	lui	$k0,0xbfc0
	lw	k0, LO_OFFS(SEAD_REVISION)(k0)
9fc000fc:	8f5a0010 	lw	$k0,16($k0)
	srl	k0, SEAD_REVISION_RTLID_SHF
9fc00100:	001ad682 	srl	$k0,$k0,0x1a
	and	k0, SEAD_REVISION_RTLID_MSK >> SEAD_REVISION_RTLID_SHF
9fc00104:	335a003f 	andi	$k0,$k0,0x3f
	xori	k0, SEAD_REVISION_RTLID_BASIC
9fc00108:	3b5a0001 	xori	$k0,$k0,0x1
	beq	k0, zero, disp_cacheerr
9fc0010c:	13400004 	beqz	$k0,9fc00120 <disp_cacheerr>
	xori	k0, SEAD_REVISION_RTLID_SOCIT101 ^ SEAD_REVISION_RTLID_BASIC
9fc00110:	3b5a0003 	xori	$k0,$k0,0x3
1:	bne	k0, zero, 1b	/* Unknown platform, so stay here */
9fc00114:	00000000 	nop
9fc00118:	1740fffe 	bnez	$k0,9fc00114 <disp_val_sead+0x1c>
	nop
9fc0011c:	00000000 	nop

9fc00120 <disp_cacheerr>:

disp_cacheerr:
	/*  CacheError occurred,  Display message 'CacheErr'.
	 *  only k0/k1 are used.
	 */
	li	k0, HIKSEG1(ATLAS_ASCIIPOS0)
9fc00120:	3c1abf00 	lui	$k0,0xbf00
	or	k1, k0
9fc00124:	037ad825 	or	$k1,$k1,$k0
	li	k0, 'C'
9fc00128:	241a0043 	li	$k0,67
	sw	k0, 0x00(k1)
9fc0012c:	af7a0000 	sw	$k0,0($k1)
	li	k0, 'a'
9fc00130:	241a0061 	li	$k0,97
	sw	k0, 0x08(k1)
9fc00134:	af7a0008 	sw	$k0,8($k1)
	li	k0, 'c'
9fc00138:	241a0063 	li	$k0,99
	sw	k0, 0x10(k1)
9fc0013c:	af7a0010 	sw	$k0,16($k1)
	li	k0, 'h'
9fc00140:	241a0068 	li	$k0,104
	sw	k0, 0x18(k1)
9fc00144:	af7a0018 	sw	$k0,24($k1)
	li	k0, 'e'
9fc00148:	241a0065 	li	$k0,101
	sw	k0, 0x20(k1)
9fc0014c:	af7a0020 	sw	$k0,32($k1)
	li	k0, 'E'
9fc00150:	241a0045 	li	$k0,69
	sw	k0, 0x28(k1)
9fc00154:	af7a0028 	sw	$k0,40($k1)
	li	k0, 'r'
9fc00158:	241a0072 	li	$k0,114
	sw	k0, 0x30(k1)
9fc0015c:	af7a0030 	sw	$k0,48($k1)
	sw	k0, 0x38(k1)
9fc00160:	af7a0038 	sw	$k0,56($k1)

1:	b	1b	/* Stay here */
9fc00164:	1000ffff 	b	9fc00164 <disp_cacheerr+0x44>
	nop
9fc00168:	00000000 	nop
	...



.org 0x200
	/* 0xBFC00200 TLB refill, 32 bit task                    */
	/*********************************************************/
1:	b	1b	/* Stay here */
9fc00200:	1000ffff 	b	9fc00200 <disp_cacheerr+0xe0>
	nop
9fc00204:	00000000 	nop
	...
	

.org 0x280
	/* 0xBFC00280 XTLB refill, 64 bit task                   */
	/*********************************************************/
1:	b	1b	/* Stay here */
9fc00280:	1000ffff 	b	9fc00280 <disp_cacheerr+0x160>
	nop
9fc00284:	00000000 	nop
	...
	

.org 0x300
	/* 0xBFC00300 Cache error exception                      */
	/*********************************************************/
	b	cacheerr /* display [CacheErr] and stay */
9fc00300:	1000ff6d 	b	9fc000b8 <cacheerr>
	nop
9fc00304:	00000000 	nop
	...
	

.org 0x380
	/* 0xBFC00380 General exception                          */
	/*********************************************************/
1:	b	1b	/* Stay here */
9fc00380:	1000ffff 	b	9fc00380 <disp_cacheerr+0x260>
	nop
9fc00384:	00000000 	nop
	...


.org 0x400
	/* 0xBFC00400 Catch interrupt exceptions, some QEDs only */
	/*********************************************************/
1:	b	1b	/* Stay here */
9fc00400:	1000ffff 	b	9fc00400 <disp_cacheerr+0x2e0>
	nop
9fc00404:	00000000 	nop
	...
	

.org 0x480
       /* 0xBFC00480 EJTAG debug exception -- don't touch ANY GPR */
       /******************************************************************
	* This exception cannot be moved from here, so below code
	* transfers it to RAM entry 0x80000300. The RAM entry will look
	* similar, which may give this sequence of machine instructions:
	*	bfc0049c:  jr    v0
	*	bfc004a0:  mfc0  v0, C0_DESAVE
	*	    (v0):  mtc0  xx, CO-DESAVE
	* Notes on hazard:
	* On CPUs without GPR interlocking, xx must be different from v0.
	* The mfc0 and mtc0 placed back to back should not be a problem,
	* as the read in CP0 takes place at an earlier stage than write,
	* and DESAVE is a scratchpad register with no operational effects.
	* Below: Two instructions between mtc0 and mfc0 is sufficient.
	*/
       mtc0     v0, C0_DESAVE
9fc00480:	4082f800 	mtc0	$v0,$31
       li       v0, KSEG0(SYS_EJTAG_RAM_VECTOR_OFS)
9fc00484:	3c028000 	lui	$v0,0x8000
9fc00488:	34420300 	ori	$v0,$v0,0x300
       jr	v0
9fc0048c:	00400008 	jr	$v0
       mfc0     v0, C0_DESAVE
9fc00490:	4002f800 	mfc0	$v0,$31
	...
9fc00500:	ffffffff 	sdc3	$31,-1($ra)
9fc00504:	80001008 	lb	$zero,4104($zero)
9fc00508:	ffffffff 	sdc3	$31,-1($ra)
9fc0050c:	ffffffff 	sdc3	$31,-1($ra)
9fc00510:	ffffffff 	sdc3	$31,-1($ra)
9fc00514:	ffffffff 	sdc3	$31,-1($ra)
9fc00518:	ffffffff 	sdc3	$31,-1($ra)
9fc0051c:	ffffffff 	sdc3	$31,-1($ra)
9fc00520:	80001000 	lb	$zero,4096($zero)
9fc00524:	ffffffff 	sdc3	$31,-1($ra)
9fc00528:	ffffffff 	sdc3	$31,-1($ra)
9fc0052c:	80001018 	lb	$zero,4120($zero)
9fc00530:	ffffffff 	sdc3	$31,-1($ra)
9fc00534:	80001010 	lb	$zero,4112($zero)
9fc00538:	80001020 	lb	$zero,4128($zero)
9fc0053c:	80001028 	lb	$zero,4136($zero)
9fc00540:	80001030 	lb	$zero,4144($zero)
9fc00544:	80001038 	lb	$zero,4152($zero)
9fc00548:	80001040 	lb	$zero,4160($zero)
9fc0054c:	80001048 	lb	$zero,4168($zero)
9fc00550:	80001050 	lb	$zero,4176($zero)
9fc00554:	80001058 	lb	$zero,4184($zero)
Disassembly of section .data: