sys_cpu_s.s

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	addiu	sp, -2*4

	/* Store return address */
	sw	ra, 0(sp)

	/* Disable interrupts (store old value of CP0 STATUS) */
	MFC0(   t0, C0_Status )
	sw	t0, 4(sp)
	li	t1, ~M_StatusIE
	and	t1, t0, t1
	MTC0(   t1, C0_Status )
		
	/* Shift to uncached */
	la	t0, sys_cpu_configurability_uncached
	KSEG1A( t0)
	jr	t0
	nop

sys_cpu_configurability_uncached:

	/* Set default = Not configurable */
	move    v0, zero

	/* Check that Config0[WC] bit is cleared */
	MFC0(   t1, C0_Config )
	li	t2, C0_CONFIG_WC_BIT
	and	t3, t1, t2
	bne	t3, zero, done
	nop

	/* Set Config0[WC] bit */
	or      t1, t2
	MTC0(   t1, C0_Config )

	/* Check Config0[8] : MMU configurability */
	li	t2, (1 << 8)
	and	t3, t1, t2
	bne	t3, zero, 1f
	nop
	/*  Config0[8] == 0 => TLB.
	 *  Try to set bit and read it back.
	 */
	or	t3, t1, t2
	MTC0(   t3, C0_Config )
	MFC0(   t3, C0_Config )
	and	t3, t3, t2
	beq	t3, zero, 1f
	nop
	/*  Bit was set, so MMU may be configured.
	 *  Clear bit and set mask.
	 */	
	MTC0(   t1, C0_Config )
	ori	v0, 1

1:
	/* Determine cache configurability
	 *
	 * Read CONFIG1 register, which holds implementation data
	 * t9 = $25
	 */
	MFC0_SEL_OPCODE( 25, R_C0_Config1, R_C0_SelConfig1 )     
#define config1	t9

	/*  Check IL (I-cache line size) field.
	 *  If 0, there is no (I)cache.
	 */
	li      t2, M_Config1IL
	and	t3, t9, t2
	beq	t3, zero, done
	nop

	/* Try to clear IL and read it back */
	li      t2, ~M_Config1IL
	and	t3, t9, t2
	MTC0_SEL_OPCODE( 11, R_C0_Config1, R_C0_SelConfig1 )  /* t3 = $11 */
	MFC0_SEL_OPCODE( 11, R_C0_Config1, R_C0_SelConfig1 )     
	li	t2, M_Config1IL
	and	t3, t2
	bne	t3, zero, done
	nop
	/*  IL was cleared, so CACHE may be configured.
	 *  Restore setting and set mask.
	 */
	MTC0_SEL_OPCODE( 25, R_C0_Config1, R_C0_SelConfig1 )
	ori     v0, 2

done:
	/* Clear WC bit */
	li	t2, ~C0_CONFIG_WC_BIT	
	and	t1, t2
	MTC0(   t1, C0_Config )

	/***** Reinitialise I-cache *****/

	/* a1 := line size (bytes) */
	la      a1, sys_icache_linesize
	lw	a1, 0(a1)

	/* a0 := cache size (bytes) */
	la      a0, sys_icache_lines
	lw	a0, 0(a0)
	multu	a0, a1
	mflo    a0

	/* Initialise */
	la	t0, sys_init_icache
	KSEG1A( t0)		/* Make it uncached */
	jal	t0
	nop
	
	/* Restore CP0 STATUS */
	lw	t0, 4(sp)
	MTC0(   t0, C0_Status )

	/* Return */
	lw	ra, 0(sp)
	jr	ra
	addiu	sp, 2*4

END( sys_cpu_configurability )
	

/************************************************************************	
 *
 *                          sys_cpu_type
 *  Description :
 *  -------------
 *
 *  Determine whether we have :
 *
 *  a) 32 or 64 bit CPU
 *  b) MIPS32/MIPS64 CPU or other type.
 *  c) Support for MIPS16e ASE or not.
 *  d) Support for EJTAG or not.
 *  e) Support for FPU or not.
 *  f) Support for level 2 cache or not.
 *  g) Support for hardware cache coherency or not.
 *
 *  Parameters :
 *  ------------
 *
 *  None

 *  Return values :
 *  ---------------
 *
 *  Following global variables are set :
 *
 *  sys_64bit
 *  sys_mips32_64
 *  sys_mips16e
 *  sys_ejtag
 *  sys_arch_rev
 *  sys_fpu
 *  sys_l2_cache
 *  sys_cpu_cache_coherency
 *
 ************************************************************************/
LEAF(sys_cpu_type)

	/* By default we assume no L2 cache */
	la	t0, sys_l2_cache
	sb	zero, 0(t0)

	/* Determine processor */
	MFC0(   t0, C0_PRId)
	li	t1, M_PRIdImp | M_PRIdCoID
	and     t0, t1

	/* MIPS 20Kc has support for hw cache coherency */
	li	t1, MIPS_20Kc
	bne	t1, t0, 1f
	move	t2, zero
	li	t2, 1
1:
	la	t1, sys_cpu_cache_coherency
	sb	t2, 0(t1)
		
	/* Check if it is a MIPS32/64 processor */	
	li      t1, M_PRIdCoID
	and	t1, t0
	srl	t1, S_PRIdCoID
	li	t2, C0_PRID_COMP_NOT_MIPS32_64
	bne	t1, t2, mips32_64
	nop

	/* Not a MIPS32/64 processor */
	la      t1, sys_mips32_64
	sb	zero, 0(t1)
	la	t1, sys_mips16e
	sb	zero, 0(t1)
	la	t1, sys_ejtag
	sb	zero, 0(t1)
	la	t1, sys_arch_rev
	sb	zero, 0(t1)
	la	t1, sys_smallpage_support
	sb	zero, 0(t1)
	
	li	t1, QED_RM52XX
	beq	t1, t0, 1f
	li	t2, 1
	li	t1, QED_RM70XX
	bne	t1, t0, 1f
	move	t2, zero	/* 32 bit, no FPU by default */
	
	/* Assume QED RM7261A */
	la	t0, sys_l2_cache_size
	li	t2, QED_RM7061A_L2_CACHE_SIZE
	sw	t2, 0(t0)

	la	t0, sys_l2_cache_linesize
	li	t2, QED_RM7061A_L2_CACHE_LSIZE
	sw	t2, 0(t0)

	la	t0, sys_l2_cache_lines
	li	t2, (QED_RM7061A_L2_CACHE_SIZE/QED_RM7061A_L2_CACHE_LSIZE)
	sw	t2, 0(t0)

	la	t0, sys_l2_cache_assoc
	li	t2, QED_RM7061A_L2_CACHE_ASSOC
	sw	t2, 0(t0)
	
	la	t0, sys_l2_cache
	li	t2, 1
	sb	t2, 0(t0)

1:
	la	t0, sys_64bit
	sb	t2, 0(t0)
	b	mips_fir_in_t1
	move	t1,t2

mips32_64:

	/* MIPS32/MIPS64 processor */
	la      t1, sys_mips32_64
	li	t0, 1
	sb	t0, 0(t1)

	MFC0(   t0, C0_Config )

	/* Determine architecture revision level */
	li	t1, M_ConfigAR
	and	t1, t0
	srl	t1, S_ConfigAR
	la	t2, sys_arch_rev
	sb	t1, 0(t2)
	
	/* Determine 32/64 based on AT field of CONFIG register */	
	li	t1, M_ConfigAT
	and	t0, t1
	srl	t0, S_ConfigAT
	li	t1, K_ConfigAT_MIPS32
	beq	t0, t1, 1f
	move	t0, zero
	li	t0, 1
1:
	la	t1, sys_64bit
	sb	t0, 0(t1)

	/* Read CONFIG1 register, which holds implementation data
	 * t0 = $8
	 */
	MFC0_SEL_OPCODE( 8, R_C0_Config1, R_C0_SelConfig1 )     

	/* Determine mips16e, ejtag, fpu support based on CONFIG1 */
	srl     t1, t0, S_Config1CA
	and	t1, 1
	la	t2, sys_mips16e
	sb	t1, 0(t2)

	srl     t1, t0, S_Config1EP
	and	t1, 1
	la	t2, sys_ejtag
	sb	t1, 0(t2)

	/* Determine small page support (requires CONFIG3 to be there) */
	sll	t1, t0, 31 - S_Config1M
	bgez	t1, 1f
	move	t1, zero
	MFC0_SEL_OPCODE( 10 /* t2 */, R_C0_Config2, R_C0_SelConfig2 )     
	sll	t1, t2, 31 - S_Config2M
	bgez	t1, 1f
	move	t1, zero
	MFC0_SEL_OPCODE( 10 /* t2 */, R_C0_Config3, R_C0_SelConfig3 )     
	srl	t1, t2, S_Config3SP
	and	t1, 1
1:
	la	t2, sys_smallpage_support
	sb	t1, 0(t2)

	/* FPU */
	srl     t1, t0, S_Config1FP
	and	t1, 1

mips_fir_in_t1:
	bne	t1, zero, 2f
	nop

	/* FPU not implemented: Clear CP0.status.FR bit */
	MFC0(   t0, C0_Status)
	li	t1, ~M_StatusFR
	and	t1, t0
	MTC0(   t1, C0_Status)
	b	1f
	move	t1, zero

2:
	/* FPU implemented: Read CP1 fir value */
	MFC0(   t0, C0_Status)
	li	t1, M_StatusCU1
	or	t1, t0
	MTC0(   t1, C0_Status)

	cfc1    t1, $0

	/* restore status reg */
	MTC0(   t0, C0_Status)
	bne	t1,zero, 1f
	nop
	or	t1, 1		/* make sure that fir != 0 */
1:
	la	t2, sys_fpu
	sw	t1, 0(t2)

        jr	ra
	nop

END(sys_cpu_type)

				
/************************************************************************	
 *
 *                          sys_cpu_l2_enable
 *  Description :
 *  -------------
 *
 *  Enable/disable L2 cache
 *
 *  a0 = 0 -> disable, else enable
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF( sys_cpu_l2_enable )

	la	t0, sys_processor
	lw	t0, 0(t0)
	li	t1, QED_RM70XX
	beq	t0, t1, 1f
	nop
	/* Only QED7061A supports L2 cache */
	jr	ra
	nop
1:	
	/* Reserve space on stack */
	addiu	sp, -8*4

	/* Store registers */
	sw	ra, 0(sp)
	sw	s0, 4(sp)
	sw	s1, 8(sp)	

	/* Copy registers to preserved registers */
	move	s0, a0

	/* Disable interrupts */
	MFC0(   s1, C0_Status )	
	li	t0, ~M_StatusIE
	and	t0, s1
	MTC0(   t0, C0_Status )
		
	/* Flush D-Cache */
	addiu	sp, -4*4
	la      t0, sys_dcache_flush_all
	jal	t0
	nop
	addiu	sp, 4*4

	/* Shift to uncached */
	la	t0, sys_cpu_l2_enable_uncached
	KSEG1A( t0)
	jr	t0
	nop

sys_cpu_l2_enable_uncached :

	beq	s0, zero, 2f
	nop

	/* Get L2 cache size */
	la	t0, sys_l2_cache_size
	lw	t0, 0(t0)
	la	t1, sys_l2_cache_linesize
	lw	t1, 0(t1)

	/* Enable L2 cache */
	MFC0(   t2, C0_Config )
	li	t3, C0_CONFIG_QED_RM70XX_SE_BIT
	or	t2, t3
	MTC0(   t2, C0_Config )	
		
	MTC0(   zero, C0_TagLo )
	MTC0(   zero, C0_TagHi )	    /* TagHi is not really used */
	
	/* Calc an address that will correspond to the first cache line */
	li	t2, KSEG0BASE
	addu	t0, t2
	subu	t0, t1		/* t0 = last line */

	/* Loop through all lines, invalidating each of them */
1:	
SET_MIPS3()
	cache	SCACHE_INDEX_STORE_TAG, 0(t2)	/* clear tag */
SET_MIPS0()
	bne	t2, t0, 1b
	addu	t2, t1

	/* Done */
	b	3f
	nop
2:		
	/* Disable L2 cache */
	MFC0(   t1, C0_Config )
	li	t0, ~C0_CONFIG_QED_RM70XX_SE_BIT
	and	t1, t0
	MTC0(   t1, C0_Config )	
3:
	/* Restore CP0 STATUS */
	MTC0(   s1, C0_Status )

	/* Restore registers */
	lw	ra, 0(sp)
	lw	s0, 4(sp)
	lw	s1, 8(sp)

	jr	ra
	addiu	sp, 8*4
	
END( sys_cpu_l2_enable )	


/************************************************************************
 *  Implementation : Static functions
 ************************************************************************/