📄 iolpc2458.h
字号:
__REG32 EP22 : 1;
__REG32 EP23 : 1;
__REG32 EP24 : 1;
__REG32 EP25 : 1;
__REG32 EP26 : 1;
__REG32 EP27 : 1;
__REG32 EP28 : 1;
__REG32 EP29 : 1;
__REG32 EP30 : 1;
__REG32 EP31 : 1;
} __dmarqstdiv_bits;
/* USB - UDCA Head Register */
typedef struct {
__REG32 : 7;
__REG32 UDCA_HEADER :25;
} __udcahead_bits;
/* USB - EP DMA Status Register */
/* USB - EP DMA Enable Register */
/* USB - EP DMA Disable Register */
typedef struct {
__REG32 EP0 : 1;
__REG32 EP1 : 1;
__REG32 EP2 : 1;
__REG32 EP3 : 1;
__REG32 EP4 : 1;
__REG32 EP5 : 1;
__REG32 EP6 : 1;
__REG32 EP7 : 1;
__REG32 EP8 : 1;
__REG32 EP9 : 1;
__REG32 EP10 : 1;
__REG32 EP11 : 1;
__REG32 EP12 : 1;
__REG32 EP13 : 1;
__REG32 EP14 : 1;
__REG32 EP15 : 1;
__REG32 EP16 : 1;
__REG32 EP17 : 1;
__REG32 EP18 : 1;
__REG32 EP19 : 1;
__REG32 EP20 : 1;
__REG32 EP21 : 1;
__REG32 EP22 : 1;
__REG32 EP23 : 1;
__REG32 EP24 : 1;
__REG32 EP25 : 1;
__REG32 EP26 : 1;
__REG32 EP27 : 1;
__REG32 EP28 : 1;
__REG32 EP29 : 1;
__REG32 EP30 : 1;
__REG32 EP31 : 1;
} __epdmadiv_bits;
/* USB - DMA Interrupt Status Register */
/* USB - DMA Interrupt Enable Register */
typedef struct {
__REG32 EOT : 1;
__REG32 NDDR : 1;
__REG32 ERR : 1;
__REG32 :29;
} __dmaintstat_bits;
/* USB - New DD Request Interrupt Status Register */
/* USB - New DD Request Interrupt Clear Register */
/* USB - New DD Request Interrupt Set Register */
/* USB - End Of Transfer Interrupt Status Register */
/* USB - End Of Transfer Interrupt Clear Register */
/* USB - End Of Transfer Interrupt Set Register */
/* USB - System Error Interrupt Status Register */
/* USB - System Error Interrupt Clear Register */
/* USB - System Error Interrupt Set Register */
typedef struct {
__REG32 EP0 : 1;
__REG32 EP1 : 1;
__REG32 EP2 : 1;
__REG32 EP3 : 1;
__REG32 EP4 : 1;
__REG32 EP5 : 1;
__REG32 EP6 : 1;
__REG32 EP7 : 1;
__REG32 EP8 : 1;
__REG32 EP9 : 1;
__REG32 EP10 : 1;
__REG32 EP11 : 1;
__REG32 EP12 : 1;
__REG32 EP13 : 1;
__REG32 EP14 : 1;
__REG32 EP15 : 1;
__REG32 EP16 : 1;
__REG32 EP17 : 1;
__REG32 EP18 : 1;
__REG32 EP19 : 1;
__REG32 EP20 : 1;
__REG32 EP21 : 1;
__REG32 EP22 : 1;
__REG32 EP23 : 1;
__REG32 EP24 : 1;
__REG32 EP25 : 1;
__REG32 EP26 : 1;
__REG32 EP27 : 1;
__REG32 EP28 : 1;
__REG32 EP29 : 1;
__REG32 EP30 : 1;
__REG32 EP31 : 1;
} __newdddiv_bits;
/* HcRevision Register */
typedef struct {
__REG32 REV : 8;
__REG32 :24;
} __hcrevision_bits;
/* HcControl Register */
typedef struct {
__REG32 CBSR : 2;
__REG32 PLE : 1;
__REG32 IE : 1;
__REG32 CLE : 1;
__REG32 BLE : 1;
__REG32 HCFS : 2;
__REG32 IR : 1;
__REG32 RWC : 1;
__REG32 RWE : 1;
__REG32 :21;
} __hccontrol_bits;
/* HcCommandStatus Register */
typedef struct {
__REG32 HCR : 1;
__REG32 CLF : 1;
__REG32 BLF : 1;
__REG32 OCR : 1;
__REG32 :12;
__REG32 SOC : 2;
__REG32 :14;
} __hccommandstatus_bits;
/* HcInterruptStatus Register */
typedef struct {
__REG32 SO : 1;
__REG32 WDH : 1;
__REG32 SF : 1;
__REG32 RD : 1;
__REG32 UE : 1;
__REG32 FNO : 1;
__REG32 RHSC : 1;
__REG32 :23;
__REG32 OC : 1;
__REG32 : 1;
} __hcinterruptstatus_bits;
/* HcInterruptEnable Register
HcInterruptDisable Register */
typedef struct {
__REG32 SO : 1;
__REG32 WDH : 1;
__REG32 SF : 1;
__REG32 RD : 1;
__REG32 UE : 1;
__REG32 FNO : 1;
__REG32 RHSC : 1;
__REG32 :23;
__REG32 OC : 1;
__REG32 MIE : 1;
} __hcinterruptenable_bits;
/* HcHCCA Register */
typedef struct {
__REG32 : 8;
__REG32 HCCA :24;
} __hchcca_bits;
/* HcPeriodCurrentED Register */
typedef struct {
__REG32 : 4;
__REG32 PCED :28;
} __hcperiodcurrented_bits;
/* HcControlHeadED Registerr */
typedef struct {
__REG32 : 4;
__REG32 CHED :28;
} __hccontrolheaded_bits;
/* HcControlCurrentED Register */
typedef struct {
__REG32 : 4;
__REG32 CCED :28;
} __hccontrolcurrented_bits;
/* HcBulkHeadED Register */
typedef struct {
__REG32 : 4;
__REG32 BHED :28;
} __hcbulkheaded_bits;
/* HcBulkCurrentED Register */
typedef struct {
__REG32 : 4;
__REG32 BCED :28;
} __hcbulkcurrented_bits;
/* HcDoneHead Register */
typedef struct {
__REG32 : 4;
__REG32 DH :28;
} __hcdonehead_bits;
/* HcFmInterval Register */
typedef struct {
__REG32 FI :14;
__REG32 : 2;
__REG32 FSMPS :15;
__REG32 FIT : 1;
} __hcfminterval_bits;
/* HcFmRemaining Register */
typedef struct {
__REG32 FR :14;
__REG32 :17;
__REG32 FRT : 1;
} __hcfmremaining_bits;
/* HcFmNumber Register */
typedef struct {
__REG32 FN :16;
__REG32 :16;
} __hcfmnumber_bits;
/* HcPeriodicStart Register */
typedef struct {
__REG32 PS :14;
__REG32 :18;
} __hcperiodicstart_bits;
/* HcLSThreshold Register */
typedef struct {
__REG32 LST :12;
__REG32 :20;
} __hclsthreshold_bits;
/* HcRhDescriptorA Register */
typedef struct {
__REG32 NDP : 8;
__REG32 PSM : 1; // ??
__REG32 NPS : 1; // ??
__REG32 DT : 1;
__REG32 OCPM : 1;
__REG32 NOCP : 1;
__REG32 :11;
__REG32 POTPGT : 8;
} __hcrhdescriptora_bits;
/* HcRhDescriptorB Register */
typedef struct {
__REG32 DR :16;
__REG32 PPCM :16;
} __hcrhdescriptorb_bits;
/* HcRhStatus Register */
typedef struct {
__REG32 LPS : 1;
__REG32 OCI : 1;
__REG32 :13;
__REG32 DRWE : 1;
__REG32 LPSC : 1;
__REG32 CCIC : 1;
__REG32 :13;
__REG32 CRWE : 1;
} __hcrhstatus_bits;
/* HcRhPortStatus[1:2] Register */
typedef struct {
__REG32 CCS : 1;
__REG32 PES : 1;
__REG32 PSS : 1;
__REG32 POCI : 1;
__REG32 PRS : 1;
__REG32 : 3;
__REG32 PPS : 1;
__REG32 LSDA : 1;
__REG32 : 6;
__REG32 CSC : 1;
__REG32 PESC : 1;
__REG32 PSSC : 1;
__REG32 OCIC : 1;
__REG32 PRSC : 1;
__REG32 :11;
} __hcrhportstatus_bits;
/* OTG_int_status Register */
typedef struct{
__REG32 TIMER_INTERRUPT_STATUS : 1;
__REG32 REMOVE_PULLUP : 1;
__REG32 HNP_FAILURE : 1;
__REG32 HNP_SUCCESS : 1;
__REG32 :28;
} __otg_int_status_bits;
/* OTG_int_enable Register */
typedef struct{
__REG32 TIMER_INTERRUPT_EN : 1;
__REG32 REMOVE_PULLUP_EN : 1;
__REG32 HNP_FAILURE_EN : 1;
__REG32 HNP_SUCCESS_EN : 1;
__REG32 :28;
} __otg_int_enable_bits;
/* OTG_int_set Register */
typedef struct{
__REG32 TIMER_INTERRUPT_SET : 1;
__REG32 REMOVE_PULLUP_SET : 1;
__REG32 HNP_FAILURE_SET : 1;
__REG32 HNP_SUCCESS_SET : 1;
__REG32 :28;
} __otg_int_set_bits;
/* OTG_int_clr Register */
typedef struct{
__REG32 TIMER_INTERRUPT_CLEAR : 1;
__REG32 REMOVE_PULLUP_CLEAR : 1;
__REG32 HNP_FAILURE_CLEAR : 1;
__REG32 HNP_SUCCESS_CLEAR : 1;
__REG32 :28;
} __otg_int_clr_bits;
/* OTG_status and control Register */
typedef struct{
__REG32 PORT_FUNCTION : 2;
__REG32 TIMER_SCALE : 2;
__REG32 TIMER_MODE : 1;
__REG32 TIMER_ENABLE : 1;
__REG32 TIMER_RESET : 1;
__REG32 TRANSPARENT_I2C_EN : 1;
__REG32 B_TO_A_HNP_TRACK : 1;
__REG32 A_TO_B_HNP_TRACK : 1;
__REG32 PULLUP_REMOVED : 1;
__REG32 : 5;
__REG32 TIMER_COUNT :16;
} __otg_stat_ctrl_bits;
/* OTG_clock Registers
OTG_status Registers */
typedef struct{
__REG32 HOST_CLK_ON : 1;
__REG32 DEV_CLK_ON : 1;
__REG32 I2C_CLK_ON : 1;
__REG32 OTG_CLK_ON : 1;
__REG32 AHB_CLK_ON : 1;
__REG32 :27;
} __otg_clock_bits;
/* OTG I2C_TX/I2C_RX Register */
typedef union{
//I2C_RX
struct {
__REG32 RX_DATA : 8;
__REG32 :24;
};
//I2C_TX
struct {
__REG32 TX_DATA : 8;
__REG32 START : 1;
__REG32 STOP : 1;
__REG32 :22;
};
} __otg_i2c_rx_tx_bits;
/* OTG I2C_STS Register */
typedef struct{
__REG32 TDI : 1;
__REG32 AFI : 1;
__REG32 NAI : 1;
__REG32 DRMI : 1;
__REG32 DRSI : 1;
__REG32 ACTIVE : 1;
__REG32 SCL : 1;
__REG32 SDA : 1;
__REG32 RFF : 1;
__REG32 RFE : 1;
__REG32 TFF : 1;
__REG32 TFE : 1;
__REG32 :20;
} __otg_i2c_sts_bits;
/* OTG I2C_CTL Register */
typedef struct{
__REG32 TDIE : 1;
__REG32 AFIE : 1;
__REG32 NAIE : 1;
__REG32 DRMIE : 1;
__REG32 DRSIE : 1;
__REG32 RFFIE : 1;
__REG32 RFDAIE : 1;
__REG32 TFFIE : 1;
__REG32 SRST : 1;
__REG32 :23;
} __otg_i2c_ctl_bits;
/* CAN acceptance filter mode register */
typedef struct {
__REG32 ACCOFF :1;
__REG32 ACCBP :1;
__REG32 EFCAN :1;
__REG32 :29;
} __afmr_bits;
/* CAN central transmit status register */
typedef struct {
__REG32 TS1 : 1;
__REG32 TS2 : 1;
__REG32 : 6;
__REG32 TBS1 : 1;
__REG32 TBS2 : 1;
__REG32 : 6;
__REG32 TCS1 : 1;
__REG32 TCS2 : 1;
__REG32 :14;
} __cantxsr_bits;
/* CAN central receive status register */
typedef struct {
__REG32 RS1 : 1;
__REG32 RS2 : 1;
__REG32 : 6;
__REG32 RBS1 : 1;
__REG32 RBS2 : 1;
__REG32 : 6;
__REG32 DOS1 : 1;
__REG32 DOS2 : 1;
__REG32 :14;
} __canrxsr_bits;
/* CAN miscellaneous status register */
typedef struct {
__REG32 ES1 : 1;
__REG32 ES2 : 1;
__REG32 : 6;
__REG32 BS1 : 1;
__REG32 BS2 : 1;
__REG32 :22;
} __canmsr_bits;
/* CAN mode register */
typedef struct {
__REG32 RM :1;
__REG32 LOM :1;
__REG32 STM :1;
__REG32 TPM :1;
__REG32 SM :1;
__REG32 RPM :1;
__REG32 :1;
__REG32 TM :1;
__REG32 :24;
} __canmod_bits;
/* CAN command register */
typedef struct {
__REG32 TR :1;
__REG32 AT :1;
__REG32 RRB :1;
__REG32 CDO :1;
__REG32 SRR :1;
__REG32 STB1 :1;
__REG32 STB2 :1;
__REG32 STB3 :1;
__REG32 :24;
} __cancmr_bits;
/* CAN global status register */
typedef struct {
__REG32 RBS :1;
__REG32 DOS :1;
__REG32 TBS :1;
__REG32 TCS :1;
__REG32 RS :1;
__REG32 TS :1;
__REG32 ES :1;
__REG32 BS :1;
__REG32 :8;
__REG32 RXERR :8;
__REG32 TXERR :8;
} __cangsr_bits;
/* CAN interrupt capture register */
typedef struct {
__REG32 RI :1;
__REG32 TI1 :1;
__REG32 EI :1;
__REG32 DOI :1;
__REG32 WUI :1;
__REG32 EPI :1;
__REG32 ALI :1;
__REG32 BEI :1;
__REG32 IDI :1;
__REG32 TI2 :1;
__REG32 TI3 :1;
__REG32 :5;
__REG32 ERRBIT :5;
__REG32 ERRDIR :1;
__REG32 ERRC :2;
__REG32 ALCBIT :8;
} __canicr_bits;
/* CAN interrupt enable register */
typedef struct {
__REG32 RIE :1;
__REG32 TIE1 :1;
__REG32 EIE :1;
__REG32 DOIE :1;
__REG32 WUIE :1;
__REG32 EPIE :1;
__REG32 ALIE :1;
__REG32 BEIE :1;
__REG32 IDIE :1;
__REG32 TIE2 :1;
__REG32 TIE3 :1;
__REG32 :21;
} __canier_bits;
/* CAN bus timing register */
typedef struct {
__REG32 BRP :10;
__REG32 :4;
__REG32 SJW :2;
__REG32 TSEG⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -