iolpc2458.h

lpc2478+ucosII

/* Back-to-Back Inter-Packet-Gap Register */
typedef struct{
__REG32 IPG       : 7;
__REG32           :25;
}__ipgt_bits;

/* Non Back-to-Back Inter-Packet-Gap Register */
typedef struct{
__REG32 IPGR      : 7;
__REG32           :25;
}__ipgr_bits;

/*Collision Window / Retry Register */
typedef struct{
__REG32 RM        : 4;
__REG32           : 4;
__REG32 CW        : 6;
__REG32           :18;
}__clrt_bits;

/* Maximum Frame Register */
typedef struct{
__REG32 MAXF      :16;
__REG32           :16;
}__maxf_bits;

/* PHY Support Register */
typedef struct{
__REG32             : 8;
__REG32 SPEED       : 1;
__REG32             : 2;
__REG32 RESET_RMII  : 1;
__REG32             :20;
}__supp_bits;

/* Test Register */
typedef struct{
__REG32 SPQ         : 1;
__REG32 TP          : 1;
__REG32 TB          : 1;
__REG32             :29;
}__test_bits;

/* MII Mgmt Configuration Register */
typedef struct{
__REG32 SI          : 1;
__REG32 SP          : 1;
__REG32 CS          : 3;
__REG32             :10;
__REG32 RSTMIIMGMT  : 1;
__REG32             :16;
}__mcfg_bits;

/* MII Mgmt Command Register */
typedef struct{
__REG32 READ        : 1;
__REG32 SCAN        : 1;
__REG32             :30;
}__mcmd_bits;

/* MII Mgmt Address Register */
typedef struct{
__REG32 REGADDR     : 5;
__REG32             : 3;
__REG32 PHY_ADDR    : 5;
__REG32             :19;
}__madr_bits;

/* MII Mgmt Write Data Register */
typedef struct{
__REG32 WRITEDATA   :16;
__REG32             :16;
}__mwtd_bits;

/* MII Mgmt Read Data Register */
typedef struct{
__REG32 READDATA    :16;
__REG32             :16;
}__mrdd_bits;

/* MII Mgmt Indicators Register */
typedef struct{
__REG32 BUSY          : 1;
__REG32 SCANNING      : 1;
__REG32 NOT_VALID     : 1;
__REG32 MII_LINC_FAIL : 1;
__REG32               :28;
}__mind_bits;

/* Station Address 0 Register */
typedef struct{
__REG32 STATION_ADDR_2  : 8;
__REG32 STATION_ADDR_1  : 8;
__REG32                 :16;
}__sa0_bits;

/* Station Address 1 Register */
typedef struct{
__REG32 STATION_ADDR_4  : 8;
__REG32 STATION_ADDR_3  : 8;
__REG32                 :16;
}__sa1_bits;

/* Station Address 2 Register */
typedef struct{
__REG32 STATION_ADDR_6  : 8;
__REG32 STATION_ADDR_5  : 8;
__REG32                 :16;
}__sa2_bits;

/* Command Register */
typedef struct{
__REG32 RXENABLE        : 1;
__REG32 TXENABLE        : 1;
__REG32                 : 1;
__REG32 REGRESET        : 1;
__REG32 TXRESET         : 1;
__REG32 RXRESET         : 1;
__REG32 PASSRUNTFRAME   : 1;
__REG32 PASSRXFILTER    : 1;
__REG32 TXFLOWCONTROL   : 1;
__REG32 RMII            : 1;
__REG32 FULLDUPLEX      : 1;
__REG32                 :21;
}__command_bits;

/* Status Register */
typedef struct{
__REG32 RXSTATUS        : 1;
__REG32 TXSTATUS        : 1;
__REG32                 :30;
}__status_bits;

/* Receive Number of Descriptors Register */
typedef struct{
__REG32 RXDESCRIPTORNUMBER  :16;
__REG32                     :16;
}__rxdescrn_bits;

/* Receive Produce Index Register */
typedef struct{
__REG32 RXPRODUCDINDEX  :16;
__REG32                 :16;
}__rxprodind_bits;

/* Receive Consume Index Register */
typedef struct{
__REG32 RXCONSUMEINDEX  :16;
__REG32                 :16;
}__rxcomind_bits;

/* Transmit Number of Descriptors Register */
typedef struct{
__REG32 TXDESCRIPTORNUMBER  :16;
__REG32                     :16;
}__txdescrn_bits;

/* Transmit Produce Index Register */
typedef struct{
__REG32 TXPRODUCDINDEX  :16;
__REG32                 :16;
}__txprodind_bits;

/* Transmit Consume Index Register */
typedef struct{
__REG32 TXCONSUMEINDEX  :16;
__REG32                 :16;
}__txcomind_bits;

/* Transmit Status Vector 0 Register */
typedef struct{
__REG32 CCR_ERR         : 1;
__REG32 LCERR           : 1;
__REG32 LOOR            : 1;
__REG32 DONE            : 1;
__REG32 MULTICAST       : 1;
__REG32 BROADCAST       : 1;
__REG32 PD              : 1;
__REG32 ED              : 1;
__REG32 EC              : 1;
__REG32 LC              : 1;
__REG32 GIANT           : 1;
__REG32 UNDERRUN        : 1;
__REG32 TB              :16;
__REG32 CF              : 1;
__REG32 PAUSE           : 1;
__REG32 BACKPRESSURE    : 1;
__REG32 VLAN            : 1;
}__tsv0_bits;

/* Transmit Status Vector 1 Register */
typedef struct{
__REG32 TBC             :16;
__REG32 TCC             : 4;
__REG32                 :12;
}__tsv1_bits;

/* Receive Status Vector Register */
typedef struct{
__REG32 RBC             :16;
__REG32 PPI             : 1;
__REG32 RXDVEPS         : 1;
__REG32 CEPS            : 1;
__REG32 RCV             : 1;
__REG32 CRC_ERR         : 1;
__REG32 LCE             : 1;
__REG32 LOOR            : 1;
__REG32 R_OK            : 1;
__REG32 MULTICAST       : 1;
__REG32 BROADCAST       : 1;
__REG32 DN              : 1;
__REG32 CF              : 1;
__REG32 PAUSE           : 1;
__REG32 UO              : 1;
__REG32 VLAN            : 1;
__REG32                 : 1;
}__rsv_bits;

/* Flow Control Counter Register */
typedef struct{
__REG32 MC              :16;
__REG32 PT              :16;
}__fwctrlcnt_bits;

/* Flow Control Status Register */
typedef struct{
__REG32 MCC             :16;
__REG32                 :16;
}__fwctrlstat_bits;

/* Receive Filter Control Register */
typedef struct{
__REG32 AUE             : 1;
__REG32 ABE             : 1;
__REG32 AME             : 1;
__REG32 AUHE            : 1;
__REG32 AMHE            : 1;
__REG32 APE             : 1;
__REG32                 : 6;
__REG32 MPEWOL          : 1;
__REG32 RXFEWOL         : 1;
__REG32                 :18;
}__rxflctrl_bits;

/* Receive Filter WoL Status Register */
typedef struct{
__REG32 AUWOL           : 1;
__REG32 ABWOL           : 1;
__REG32 AMWOL           : 1;
__REG32 AUHWOL          : 1;
__REG32 AMHWOL          : 1;
__REG32 APWOL           : 1;
__REG32                 : 1;
__REG32 RXFWOL          : 1;
__REG32 MPWOL           : 1;
__REG32                 :23;
}__rxflwolstat_bits;

/* Receive Filter WoL Clear Register */
typedef struct{
__REG32 AUWOLC          : 1;
__REG32 ABWOLC          : 1;
__REG32 AMWOLC          : 1;
__REG32 AUHWOLC         : 1;
__REG32 AMHWOLC         : 1;
__REG32 APWOLC          : 1;
__REG32                 : 1;
__REG32 RXFWOLC         : 1;
__REG32 MPWOLC          : 1;
__REG32                 :23;
}__rxflwolclr_bits;

/* Interrupt Status Register */
typedef struct{
__REG32 RXOVERRUNINT    : 1;
__REG32 RXERRORINT      : 1;
__REG32 RXFINISHEDINT   : 1;
__REG32 RXDONEINT       : 1;
__REG32 TXUNDERRUNINT   : 1;
__REG32 TXERRORINT      : 1;
__REG32 TXFINISHEDINT   : 1;
__REG32 TXDONEINT       : 1;
__REG32                 : 4;
__REG32 SOFTINT         : 1;
__REG32 WAKEUPINT       : 1;
__REG32                 :18;
}__intstat_bits;

/* Interrupt Enable Register */
typedef struct{
__REG32 RXOVERRUNINTEN  : 1;
__REG32 RXERRORINTEN    : 1;
__REG32 RXFINISHEDINTEN : 1;
__REG32 RXDONEINTEN     : 1;
__REG32 TXUNDERRUNINTEN : 1;
__REG32 TXERRORINTEN    : 1;
__REG32 TXFINISHEDINTEN : 1;
__REG32 TXDONEINTEN     : 1;
__REG32                 : 4;
__REG32 SOFTINTEN       : 1;
__REG32 WAKEUPINTEN     : 1;
__REG32                 :18;
}__intena_bits;

/* Interrupt Clear Register */
typedef struct{
__REG32 RXOVERRUNINTCLR : 1;
__REG32 RXERRORINTCLR   : 1;
__REG32 RXFINISHEDINTCLR: 1;
__REG32 RXDONEINTCLR    : 1;
__REG32 TXUNDERRUNINTCLR: 1;
__REG32 TXERRORINTCLR   : 1;
__REG32 TXFINISHEDINTCLR: 1;
__REG32 TXDONEINTCLR    : 1;
__REG32                 : 4;
__REG32 SOFTINTCLR      : 1;
__REG32 WAKEUPINTCLR    : 1;
__REG32                 :18;
}__intclr_bits;

/* Interrupt Set Register */
typedef struct{
__REG32 RXOVERRUNINTSET : 1;
__REG32 RXERRORINTSET   : 1;
__REG32 RXFINISHEDINTSET: 1;
__REG32 RXDONEINTSET    : 1;
__REG32 TXUNDERRUNINTSET: 1;
__REG32 TXERRORINTSET   : 1;
__REG32 TXFINISHEDINTSET: 1;
__REG32 TXDONEINTSET    : 1;
__REG32                 : 4;
__REG32 SOFTINTSET      : 1;
__REG32 WAKEUPINTSET    : 1;
__REG32                 :18;
}__intset_bits;

/* Power Down Register */
typedef struct{
__REG32                 :31;
__REG32 POWERDOWN       : 1;
}__pwrdn_bits;

/* USB - Device Interrupt Status Register */
typedef struct {
  __REG32 USB_INT_REQ_LP    : 1;
  __REG32 USB_INT_REQ_HP    : 1;
  __REG32 USB_INT_REQ_DMA   : 1;
  __REG32 USB_HOST_INT      : 1;
  __REG32 USB_ATX_INT       : 1;
  __REG32 USB_OTG_TIMER_INT : 1;
  __REG32 USB_I2C_INT       : 1;
  __REG32                   : 1;
  __REG32 USB_NEED_CLOCK    : 1;
  __REG32                   :22;
  __REG32 EN_USB_INTS       : 1;
} __usbints_bits;

/* USB - Device Interrupt Status Register */
/* USB - Device Interrupt Enable Register */
/* USB - Device Interrupt Clear Register */
/* USB - Device Interrupt Set Register */
typedef struct {
  __REG32 FRAME             : 1;
  __REG32 EP_FAST           : 1;
  __REG32 EP_SLOW           : 1;
  __REG32 DEV_STAT          : 1;
  __REG32 CCEMTY            : 1;
  __REG32 CDFULL            : 1;
  __REG32 RXENDPKT          : 1;
  __REG32 TXENDPKT          : 1;
  __REG32 EP_RLZED          : 1;
  __REG32 ERR_INT           : 1;
  __REG32                   :22;
} __devints_bits;

/* USB - Device Interrupt Priority Register */
typedef struct {
  __REG8  FRAME             : 1;
  __REG8  EP_FAST           : 1;
  __REG8                    : 6;
} __devintpri_bits;

/* USB - Endpoint Interrupt Status Register */
/* USB - Endpoint Interrupt Enable Register */
/* USB - Endpoint Interrupt Clear Register */
/* USB - Endpoint Interrupt Set Register */
/* USB - Endpoint Interrupt Priority Register */
typedef struct {
  __REG32 EP_0RX            : 1;
  __REG32 EP_0TX            : 1;
  __REG32 EP_1RX            : 1;
  __REG32 EP_1TX            : 1;
  __REG32 EP_2RX            : 1;
  __REG32 EP_2TX            : 1;
  __REG32 EP_3RX            : 1;
  __REG32 EP_3TX            : 1;
  __REG32 EP_4RX            : 1;
  __REG32 EP_4TX            : 1;
  __REG32 EP_5RX            : 1;
  __REG32 EP_5TX            : 1;
  __REG32 EP_6RX            : 1;
  __REG32 EP_6TX            : 1;
  __REG32 EP_7RX            : 1;
  __REG32 EP_7TX            : 1;
  __REG32 EP_8RX            : 1;
  __REG32 EP_8TX            : 1;
  __REG32 EP_9RX            : 1;
  __REG32 EP_9TX            : 1;
  __REG32 EP_10RX           : 1;
  __REG32 EP_10TX           : 1;
  __REG32 EP_11RX           : 1;
  __REG32 EP_11TX           : 1;
  __REG32 EP_12RX           : 1;
  __REG32 EP_12TX           : 1;
  __REG32 EP_13RX           : 1;
  __REG32 EP_13TX           : 1;
  __REG32 EP_14RX           : 1;
  __REG32 EP_14TX           : 1;
  __REG32 EP_15RX           : 1;
  __REG32 EP_15TX           : 1;
} __endpints_bits;

/* USB - Realize Enpoint Register */
typedef struct {
  __REG32 EP0               : 1;
  __REG32 EP1               : 1;
  __REG32 EP2               : 1;
  __REG32 EP3               : 1;
  __REG32 EP4               : 1;
  __REG32 EP5               : 1;
  __REG32 EP6               : 1;
  __REG32 EP7               : 1;
  __REG32 EP8               : 1;
  __REG32 EP9               : 1;
  __REG32 EP10              : 1;
  __REG32 EP11              : 1;
  __REG32 EP12              : 1;
  __REG32 EP13              : 1;
  __REG32 EP14              : 1;
  __REG32 EP15              : 1;
  __REG32 EP16              : 1;
  __REG32 EP17              : 1;
  __REG32 EP18              : 1;
  __REG32 EP19              : 1;
  __REG32 EP20              : 1;
  __REG32 EP21              : 1;
  __REG32 EP22              : 1;
  __REG32 EP23              : 1;
  __REG32 EP24              : 1;
  __REG32 EP25              : 1;
  __REG32 EP26              : 1;
  __REG32 EP27              : 1;
  __REG32 EP28              : 1;
  __REG32 EP29              : 1;
  __REG32 EP30              : 1;
  __REG32 EP31              : 1;
} __realizeendp_bits;

/* USB - Endpoint Index Register */
typedef struct {
  __REG32 PHY_ENDP          : 5;
  __REG32                   :27;
} __endpind_bits;

/* USB - MaxPacketSize Register */
typedef struct {
  __REG32 MAXPACKETSIZE     :10;
  __REG32                   :22;
} __maxpacksize_bits;

/* USB - Receive Packet Length Register */
typedef struct {
  __REG32 PKT_LNGTH         :10;
  __REG32 DV                : 1;
  __REG32 PKT_RDY           : 1;
  __REG32                   :20;
} __rcvepktlen_bits;

/* USB - Transmit Packet Length Register */
typedef struct {
  __REG32 PKT_LNGHT         :10;
  __REG32                   :22;
} __transmitpktlen_bits;

/* USB - Control Register */
typedef struct {
  __REG32 RD_EN             : 1;
  __REG32 WR_EN             : 1;
  __REG32 LOG_ENDPOINT      : 4;
  __REG32                   :26;
} __usbctrl_bits;

/* USB - Command Code Register */
typedef struct {
  __REG32                   : 8;
  __REG32 CMD_PHASE         : 8;
  __REG32 CMD_CODE          : 8;
  __REG32                   : 8;
} __cmdcode_bits;

/* USB - Command Data Register */
typedef struct {
  __REG32 CMD_DATA          : 8;
  __REG32                   :24;
} __cmddata_bits;

/* USB - DMA Request Status Register */
/* USB - DMA Request Clear Register */
/* USB - DMA Request Set Regiser */
typedef struct {
  __REG32 EP0               : 1;
  __REG32 EP1               : 1;
  __REG32 EP2               : 1;
  __REG32 EP3               : 1;
  __REG32 EP4               : 1;
  __REG32 EP5               : 1;
  __REG32 EP6               : 1;
  __REG32 EP7               : 1;
  __REG32 EP8               : 1;
  __REG32 EP9               : 1;
  __REG32 EP10              : 1;
  __REG32 EP11              : 1;
  __REG32 EP12              : 1;
  __REG32 EP13              : 1;
  __REG32 EP14              : 1;
  __REG32 EP15              : 1;
  __REG32 EP16              : 1;
  __REG32 EP17              : 1;
  __REG32 EP18              : 1;
  __REG32 EP19              : 1;
  __REG32 EP20              : 1;
  __REG32 EP21              : 1;