at91.h

avr上的RTOS

#define TC_BCR          (TC_BASE + 0xC0)        /*!< \brief Block control register address. */
#define TC_SYNC                 0x00000001      /*!< \brief Synchronisation trigger */
/*@}*/

/*! \name Timer Counter Block Mode Register */
/*@{*/
#define TC_BMR          (TC_BASE + 0xC4)        /*!< \brief Block mode register address. */
#define TC_TC0XC0S              0x00000003      /*!< \brief External clock signal 0 selection mask. */
#define TC_TCLK0XC0             0x00000000      /*!< \brief Selects TCLK0. */
#define TC_NONEXC0              0x00000001      /*!< \brief None selected. */
#define TC_TIOA1XC0             0x00000002      /*!< \brief Selects TIOA1. */
#define TC_TIOA2XC0             0x00000003      /*!< \brief Selects TIOA2. */

#define TC_TC1XC1S              0x0000000C      /*!< \brief External clock signal 1 selection mask. */
#define TC_TCLK1XC1             0x00000000      /*!< \brief Selects TCLK1. */
#define TC_NONEXC1              0x00000004      /*!< \brief None selected. */
#define TC_TIOA0XC1             0x00000008      /*!< \brief Selects TIOA0. */
#define TC_TIOA2XC1             0x0000000C      /*!< \brief Selects TIOA2. */

#define TC_TC2XC2S              0x00000030      /*!< \brief External clock signal 2 selection mask. */
#define TC_TCLK2XC2             0x00000000      /*!< \brief Selects TCLK2. */
#define TC_NONEXC2              0x00000010      /*!< \brief None selected. */
#define TC_TIOA0XC2             0x00000020      /*!< \brief Selects TIOA0. */
#define TC_TIOA1XC2             0x00000030      /*!< \brief Selects TIOA1. */
/*@}*/

/*@} xgNutArchArmAt91Tc */

/*!
 * \addtogroup xgNutArchArmAt91Pio
 */
/*@{*/
#define PIO_BASE    0xFFFF0000  /*!< \brief PIO base address. */
#define PIO_PER     (PIO_BASE + 0x00)   /*!< \brief PIO enable register. */
#define PIO_PDR     (PIO_BASE + 0x04)   /*!< \brief PIO disable register. */
#define PIO_PSR     (PIO_BASE + 0x08)   /*!< \brief PIO status register. */
#define PIO_OER     (PIO_BASE + 0x10)   /*!< \brief Output enable register. */
#define PIO_ODR     (PIO_BASE + 0x14)   /*!< \brief Output disable register. */
#define PIO_OSR     (PIO_BASE + 0x18)   /*!< \brief Output status register. */
#define PIO_IFER    (PIO_BASE + 0x20)   /*!< \brief Input filter enable register. */
#define PIO_IFDR    (PIO_BASE + 0x24)   /*!< \brief Input filter disable register. */
#define PIO_IFSR    (PIO_BASE + 0x28)   /*!< \brief Input filter status register. */
#define PIO_SODR    (PIO_BASE + 0x30)   /*!< \brief Set output data register. */
#define PIO_CODR    (PIO_BASE + 0x34)   /*!< \brief Clear output data register. */
#define PIO_ODSR    (PIO_BASE + 0x38)   /*!< \brief Output data status register. */
#define PIO_PDSR    (PIO_BASE + 0x3C)   /*!< \brief Pin data status register. */
#define PIO_IER     (PIO_BASE + 0x40)   /*!< \brief Interrupt enable register. */
#define PIO_IDR     (PIO_BASE + 0x44)   /*!< \brief Interrupt disable register. */
#define PIO_IMR     (PIO_BASE + 0x48)   /*!< \brief Interrupt mask register. */
#define PIO_ISR     (PIO_BASE + 0x4C)   /*!< \brief Interrupt status register. */

/*@} xgNutArchArmAt91Pio */

/*!
 * \addtogroup xgNutArchArmAt91Ps
 */
/*@{*/
#define PS_BASE     0xFFFF4000  /*!< \brief PS base address. */

/*!
 * \name PS Control Register
 */
/*@{*/

/*! \brief Register address.
 *
 * This register allows to stop the CPU clock. The clock is automatically
 * enabled after reset and by any interrupt.
 */
#define PS_CR       (PS_BASE + 0x00)
/*@}*/

/*!
 * \name Peripheral Clock Control Registers
 */
/*@{*/
#define PS_PCER     (PS_BASE + 0x04)    /*!< \brief Peripheral clock enable register address. */
#define PS_PCDR     (PS_BASE + 0x08)    /*!< \brief Peripheral clock disable register address. */
#define PS_PCSR     (PS_BASE + 0x0C)    /*!< \brief Peripheral clock status register address. */
/*@}*/

/*@} xgNutArchArmAt91Ps */

/*!
 * \addtogroup xgNutArchArmAt91Wd
 */
/*@{*/
#define WD_BASE     0xFFFF8000  /*!< \brief Watch Dog register base address. */

/*! \name Watch Dog Overflow Mode Register */
/*@{*/
#define WD_OMR          (WD_BASE + 0x00)        /*!< \brief Overflow mode register address. */
#define WD_WDEN                 0x00000001      /*!< \brief Watch Dog enable. */
#define WD_RSTEN                0x00000002      /*!< \brief Internal reset enable. */
#define WD_IRQEN                0x00000004      /*!< \brief Interrupt enable. */
#define WD_EXTEN                0x00000008      /*!< \brief External signal enable. */
#define WD_OKEY                 0x00002340      /*!< \brief Overflow mode register access key. */
/*@}*/

/*! \name Watch Dog Clock Register */
/*@{*/
#define WD_CMR          (WD_BASE + 0x04)        /*!< \brief Clock mode register address. */
#define WD_WDCLKS               0x00000003      /*!< \brief Clock selection mask. */
#define WD_WDCLKS_MCK8          0x00000000      /*!< \brief Selects MCK/8. */
#define WD_WDCLKS_MCK32         0x00000001      /*!< \brief Selects MCK/32. */
#define WD_WDCLKS_MCK128        0x00000002      /*!< \brief Selects MCK/128. */
#define WD_WDCLKS_MCK1024       0x00000003      /*!< \brief Selects MCK/1024. */
#define WD_HPCV                 0x0000003C      /*!< \brief High preload counter value. */
#define WD_CKEY                 (0x06E<<7)      /*!< \brief Clock register access key. */
/*@}*/

/*! \name Watch Dog Control Register */
/*@{*/
#define WD_CR           (WD_BASE + 0x08)        /*!< \brief Control register address. */
#define WD_RSTKEY               0x0000C071      /*!< \brief Watch Dog restart key. */
/*@}*/

/*! \name Watch Dog Status Register */
/*@{*/
#define WD_SR           (WD_BASE + 0x0C)        /*!< \brief Status register address. */
#define WD_WDOVF                0x00000001      /*!< \brief Watch Dog overflow status. */
/*@}*/

/*@} xgNutArchArmAt91Wd */

/*!
 * \addtogroup xgNutArchArmAt91Aic
 */
/*@{*/
#define AIC_BASE    0xFFFFF000  /*!< AIC base address. */

/*! \name Interrupt Source Mode Registers */
/*@{*/
/*! \brief Source mode register array.
 */
#define AIC_SMR(i)  (AIC_BASE + i * 4)

/*! \brief Priority mask. 
 *
 * Priority levels can be between 0 (lowest) and 7 (highest).
 */
#define AIC_PRIOR                       0x00000007

/*! \brief Interrupt source type mask. 
 *
 * Internal interrupts can level sensitive or edge triggered.
 *
 * External interrupts can triggered on positive or negative levels or 
 * on rising or falling edges.
 */
#define AIC_SRCTYPE                     0x00000060

#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00000000      /*!< \brief Internal level sensitive. */
#define AIC_SRCTYPE_INT_EDGE_TRIGGERED  0x00000020      /*!< \brief Internal edge triggered. */
#define AIC_SRCTYPE_EXT_LOW_LEVEL       0x00000000      /*!< \brief External low level. */
#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE   0x00000020      /*!< \brief External falling edge. */
#define AIC_SRCTYPE_EXT_HIGH_LEVEL      0x00000040      /*!< \brief External high level. */
#define AIC_SRCTYPE_EXT_POSITIVE_EDGE   0x00000060      /*!< \brief External rising edge. */
/*@}*/

/*! \name Interrupt Source Vector Registers */
/*@{*/
/*! \brief Source vector register array. 
 *
 * Stores the addresses of the corresponding interrupt handlers.
 */
#define AIC_SVR(i)  (AIC_BASE + 0x80 + i * 4)
/*@}*/

/*! \name Interrupt Vector Register */
/*@{*/
#define AIC_IVR     (AIC_BASE + 0x100)  /*!< \brief IRQ vector register address. */
/*@}*/

/*! \name Fast Interrupt Vector Register */
/*@{*/
#define AIC_FVR     (AIC_BASE + 0x104)  /*!< \brief FIQ vector register address. */
/*@}*/

/*! \name Interrupt Status Register */
/*@{*/
#define AIC_ISR     (AIC_BASE + 0x108)  /*!< \brief Interrupt status register address. */
#define AIC_IRQID               0x0000001F      /*!< \brief Current interrupt identifier mask. */
/*@}*/

/*! \name Interrupt Pending Register */
/*@{*/
#define AIC_IPR     (AIC_BASE + 0x10C)  /*!< \brief Interrupt pending register address. */
/*@}*/

/*! \name Interrupt Mask Register */
/*@{*/
#define AIC_IMR     (AIC_BASE + 0x110)  /*!< \brief Interrupt mask register address. */
/*@}*/

/*! \name Interrupt Core Status Register */
/*@{*/
#define AIC_CISR    (AIC_BASE + 0x114)  /*!< \brief Core interrupt status register address. */
#define AIC_NFIQ                0x00000001      /*!< \brief Core FIQ Status */
#define AIC_NIRQ                0x00000002      /*!< \brief Core IRQ Status */
/*@}*/

/*! \name Interrupt Enable Command Register */
/*@{*/
#define AIC_IECR    (AIC_BASE + 0x120)  /*!< \brief Interrupt enable command register address. */
/*@}*/

/*! \name Interrupt Disable Command Register */
/*@{*/
#define AIC_IDCR    (AIC_BASE + 0x124)  /*!< \brief Interrupt disable command register address. */
/*@}*/

/*! \name Interrupt Clear Command Register */
/*@{*/
#define AIC_ICCR    (AIC_BASE + 0x128)  /*!< \brief Interrupt clear command register address. */
/*@}*/

/*! \name Interrupt Set Command Register */
/*@{*/
#define AIC_ISCR    (AIC_BASE + 0x12C)  /*!< \brief Interrupt set command register address. */
/*@}*/

/*! \name End Of Interrupt Command Register */
/*@{*/
#define AIC_EOICR   (AIC_BASE + 0x130)  /*!< \brief End of interrupt command register address. */
/*@}*/

/*! \name Spurious Interrupt Vector Register */
/*@{*/
#define AIC_SPU     (AIC_BASE + 0x134)  /*!< \brief Spurious vector register address. */
/*@}*/

/*!
 * \brief Interrupt entry.
 */
#define IRQ_ENTRY() \
    asm volatile("sub   lr, lr,#4"          "\n\t"  /* Adjust LR */ \
                 "stmfd sp!,{r0-r12,lr}"    "\n\t"  /* Save registers on IRQ stack. */ \
                 "mrs   r1, spsr"           "\n\t"  /* Save SPSR */ \
                 "stmfd sp!,{r1}"           "\n\t")     /* */

/*!
 * \brief Interrupt exit.
 */
#define IRQ_EXIT() \
    asm volatile("ldmfd sp!, {r1}"          "\n\t"  /* Restore SPSR */ \
                 "msr   spsr_c, r1"         "\n\t"  /* */ \
                 "ldr   r0, =0xFFFFF000"    "\n\t"  /* End of interrupt. */ \
                 "str   r0, [r0, #0x130]"   "\n\t"  /* */ \
                 "ldmfd sp!, {r0-r12, pc}^" "\n\t")     /* Restore registers and return. */


/*@} xgNutArchArmAt91Aic */

/*! \addtogroup xgNutArchArmAt91 */
/*@{*/

/*! \name Peripheral Identifiers and Interrupts */
/*@{*/
#define FIQ_ID      0           /*!< \brief Fast interrupt ID. */
#define SWIRQ_ID    1           /*!< \brief Software interrupt ID. */
#define US0_ID      2           /*!< \brief USART 0 ID. */
#define US1_ID      3           /*!< \brief USART 1 ID. */
#define TC0_ID      4           /*!< \brief Timer 0 ID. */
#define TC1_ID      5           /*!< \brief Timer 1 ID. */
#define TC2_ID      6           /*!< \brief Timer 2 ID. */
#define WDI_ID      7           /*!< \brief Watchdog interrupt ID. */
#define PIO_ID      8           /*!< \brief Parallel I/O controller ID. */
#define IRQ0_ID     16          /*!< \brief External interrupt 0 ID. */
#define IRQ1_ID     17          /*!< \brief External interrupt 1 ID. */
#define IRQ2_ID     18          /*!< \brief External interrupt 2 ID. */
/*@}*/
/*@} xgNutArchArmAt91 */

#endif                          /* _ARCH_ARM_AT91_H_ */