at91.h

avr上的RTOS

#ifndef _ARCH_ARM_AT91_H_
#define _ARCH_ARM_AT91_H_

/*
 * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * For additional information see http://www.ethernut.de/
 */

/*!
 * \file arch/arm/at91.h
 * \brief AT91 peripherals.
 *
 * \verbatim
 *
 * $Log: at91.h,v $
 * Revision 1.2  2005/11/20 14:44:14  haraldkipp
 * Register offsets added.
 *
 * Revision 1.1  2005/10/24 10:31:13  haraldkipp
 * Moved from parent directory.
 *
 *
 * \endverbatim
 */

/*!
 * \addtogroup xgNutArchArmAt91Ebi
 */
/*@{*/

#define EBI_BASE                0xFFE00000      /*!< \brief EBI base address. */

/*! \name Chip Select Register */
/*@{*/
#define EBI_CSR(i)      (EBI_BASE + i * 4)      /*!< \brief Chip select register address. */

#define EBI_DBW                 0x00000003      /*!< \brief Masks data bus width. */
#define EBI_DBW_16              0x00000001      /*!< \brief 16-bit data bus width. */
#define EBI_DBW_8               0x00000002      /*!< \brief 8-bit data bus width. */

#define EBI_NWS                 0x0000001C      /*!< \brief Masks number of wait states. */
#define EBI_NWS_1               0x00000000      /*!< \brief 1 wait state. */
#define EBI_NWS_2               0x00000004      /*!< \brief 2 wait states. */
#define EBI_NWS_3               0x00000008      /*!< \brief 3 wait states. */
#define EBI_NWS_4               0x0000000C      /*!< \brief 4 wait states. */
#define EBI_NWS_5               0x00000010      /*!< \brief 5 wait states. */
#define EBI_NWS_6               0x00000014      /*!< \brief 6 wait states. */
#define EBI_NWS_7               0x00000018      /*!< \brief 7 wait states. */
#define EBI_NWS_8               0x0000001C      /*!< \brief 8 wait states. */

#define EBI_WSE                 0x00000020      /*!< \brief Wait state enable. */

#define EBI_PAGES               0x00000180      /*!< \brief Page size mask. */
#define EBI_PAGES_1M            0x00000000      /*!< \brief 1 MByte page size. */
#define EBI_PAGES_4M            0x00000080      /*!< \brief 4 MBytes page size. */
#define EBI_PAGES_16M           0x00000100      /*!< \brief 16 MBytes page size. */
#define EBI_PAGES_64M           0x00000180      /*!< \brief 64 MBytes page size. */

#define EBI_TDF                 0x00000E00      /*!< \brief Masks data float output time clock cycles. */
#define EBI_TDF_0               0x00000000      /*!< \brief No added cycles. */
#define EBI_TDF_1               0x00000200      /*!< \brief 1 cycle. */
#define EBI_TDF_2               0x00000400      /*!< \brief 2 cycles. */
#define EBI_TDF_3               0x00000600      /*!< \brief 3 cycles. */
#define EBI_TDF_4               0x00000800      /*!< \brief 4 cycles. */
#define EBI_TDF_5               0x00000A00      /*!< \brief 5 cycles. */
#define EBI_TDF_6               0x00000C00      /*!< \brief 6 cycles. */
#define EBI_TDF_7               0x00000E00      /*!< \brief 7 cycles. */

#define EBI_BAT                 0x00001000      /*!< \brief Byte access type */
#define EBI_BAT_BYTE_WRITE      0x00000000      /*!< \brief Byte write access type */
#define EBI_BAT_BYTE_SELECT     0x00001000      /*!< \brief Byte select access type */

#define EBI_CSEN                0x00002000      /*!< \brief Chip select enable */

#define EBI_BA                  0xFFF00000      /*!< \brief Page base address mask. */
/*@}*/

/*! \name Remap Control Register */
/*@{*/
#define EBI_RCR         (EBI_BASE + 0x20)       /*!< \brief Remap control register address. */
#define EBI_RCB                 0x00000001      /*!< \brief Remap command. */
/*@}*/

/*! \name Memory Control Register */
/*@{*/
#define EBI_MCR         (EBI_BASE + 0x24)       /*!< \brief Memory control register address. */
#define EBI_ALE                 0x00000007      /*!< \brief Address line enable */
#define EBI_ALE_16M             0x00000000      /*!< \brief 16 Mbytes total address space. */
#define EBI_ALE_8M              0x00000004      /*!< \brief 8 Mbytes total address space. */
#define EBI_ALE_4M              0x00000005      /*!< \brief 4 Mbytes total address space. */
#define EBI_ALE_2M              0x00000006      /*!< \brief 2 Mbytes total address space. */
#define EBI_ALE_1M              0x00000007      /*!< \brief 1 Mbyte total address space. */

#define EBI_DRP                 0x00000010      /*!< \brief Data read protocol mask. */
#define EBI_DRP_STANDARD        0x00000000      /*!< \brief Standard read protocol. */
#define EBI_DRP_EARLY           0x00000010      /*!< \brief Early read protocol. */
/*@}*/

/*@} xgNutArchArmAt91Ebi */

/*!
 * \addtogroup xgNutArchArmAt91Sf
 */
/*@{*/

#define SF_BASE                 0xFFF00000      /*!< \brief Special function register base address. */

/*! \name Chip Identification Registers */
/*@{*/
#define SF_CIDR         (SF_BASE + 0x00)        /*!< \brief Chip ID register address. */
#define SF_EXID         (SF_BASE + 0x04)        /*!< \brief Chip ID extension register address. */
#define SF_VERSION              0x0000001F      /*!< \brief Version number mask. */

#define SF_NVPSIZ               0x00000F00      /*!< \brief Masks non volatile program memory size. */
#define SF_NVPSIZ_NONE          0x00000000      /*!< \brief No NV program memory. */
#define SF_NVPSIZ_32K           0x00000300      /*!< \brief 32 kBytes NV program memory. */
#define SF_NVPSIZ_64K           0x00000500      /*!< \brief 64 kBytes NV program memory. */
#define SF_NVPSIZ_128K          0x00000700      /*!< \brief 128 kBytes NV program memory. */
#define SF_NVPSIZ_256K          0x00000900      /*!< \brief 256 kBytes NV program memory. */

#define SF_NVDSIZ               0x0000F000      /*!< \brief Masks non volatile data memory size. */
#define SF_NVDSIZ_NONE          0x00000000      /*!< \brief No NV data memory. */

#define SF_VDSIZ                0x000F0000      /*!< \brief Masks volatile data memory size. */
#define SF_VDSIZ_NONE           0x00000000      /*!< \brief No volatile data memory. */
#define SF_VDSIZ_1K             0x00010000      /*!< \brief 1 kBytes volatile data memory. */
#define SF_VDSIZ_2K             0x00020000      /*!< \brief 2 kBytes volatile data memory. */
#define SF_VDSIZ_4K             0x00040000      /*!< \brief 4 kBytes volatile data memory. */
#define SF_VDSIZ_8K             0x00080000      /*!< \brief 8 kBytes volatile data memory. */

#define SF_ARCH                 0x0FF00000      /*!< \brief Architecture code mask. */
#define SF_ARCH_AT91x40         0x04000000      /*!< \brief AT91x40 architecture. */
#define SF_ARCH_AT91x55         0x05500000      /*!< \brief AT91x55 architecture. */
#define SF_ARCH_AT91x63         0x06300000      /*!< \brief AT91x63 architecture. */

#define SF_NVPTYP               0x70000000      /*!< \brief Masks non volatile program memory type. */
#define SF_NVPTYP_M             0x01000000      /*!< \brief M or F series. */
#define SF_NVPTYP_C             0x02000000      /*!< \brief C series. */
#define SF_NVPTYP_S             0x03000000      /*!< \brief S series. */
#define SF_NVPTYP_R             0x04000000      /*!< \brief R series. */

#define SF_EXT                  0x80000000      /*!< \brief Extension flag. */

/*@}*/

/*! \name Reset Status Flag Register */
/*@{*/
#define SF_RSR          (SF_BASE + 0x08)        /*!< \brief Reset status register address. */
#define SF_EXT_RESET            0x0000006C      /*!< \brief Reset caused by external pin. */
#define SF_WD_RESET             0x00000053      /*!< \brief Reset caused by internal watch dog. */
/*@}*/

/*! \name Memory Mode Register */
/*@{*/
#define SF_MMR          (SF_BASE + 0x0C)        /*!< \brief Memory mode register address. */
#define SF_RAMWU                0x00000001      /*!< \brief Internal extended RAM write allowed. */
/*@}*/

/*! \name Protect Mode Register */
/*@{*/
#define SF_PMR          (SF_BASE + 0x18)        /*!< \brief Protect mode register address. */
#define SF_AIC                  0x00000020      /*!< \brief AIC runs in protect mode. */
/*@}*/

/*@} xgNutArchArmAt91Sf */

/*!
 * \addtogroup xgNutArchArmAt91Us
 */
/*@{*/

#define USART1_BASE             0xFFFCC000      /*!< \brief USART 1 base address. */
#define USART0_BASE             0xFFFD0000      /*!< \brief USART 0 base address. */

/*! \name USART Control Register */
/*@{*/
#define US_CR_OFF               0x00000000      /*!< \brief USART control register offset. */
#define US0_CR  (USART0_BASE + US_CR_OFF)       /*!< \brief Channel 0 control register address. */
#define US1_CR  (USART1_BASE + US_CR_OFF)       /*!< \brief Channel 1 control register address. */
#define US_RSTRX                0x00000004      /*!< \brief Reset receiver */
#define US_RSTTX                0x00000008      /*!< \brief Reset transmitter */
#define US_RXEN                 0x00000010      /*!< \brief Receiver enable */
#define US_RXDIS                0x00000020      /*!< \brief Receiver disable */
#define US_TXEN                 0x00000040      /*!< \brief Transmitter enable */
#define US_TXDIS                0x00000080      /*!< \brief Transmitter disable */
#define US_RSTSTA               0x00000100      /*!< \brief Reset status bits */
#define US_STTBRK               0x00000200      /*!< \brief Start break */
#define US_STPBRK               0x00000400      /*!< \brief Stop break */
#define US_STTTO                0x00000800      /*!< \brief Start timeout */
#define US_SENDA                0x00001000      /*!< \brief Send next byte with address bit set. */
/*@}*/

/*! \name Mode Register */
/*@{*/
#define US_MR_OFF               0x00000004      /*!< \brief USART mode register offset. */
#define US0_MR  (USART0_BASE + US_MR_OFF)       /*!< \brief Channel 0 mode register address. */
#define US1_MR  (USART1_BASE + US_MR_OFF)       /*!< \brief Channel 1 mode register address. */

#define US_CLKS                 0x00000030      /*!< \brief Clock selection mask. */
#define US_CLKS_MCK             0x00000000      /*!< \brief Master clock. */
#define US_CLKS_MCK8            0x00000010      /*!< \brief Master clock divided by 8. */
#define US_CLKS_SCK             0x00000020      /*!< \brief External clock. */
#define US_CLKS_SLCK            0x00000030      /*!< \brief Slow clock. */

#define US_CHRL                 0x000000C0      /*!< \brief Masks data length. */
#define US_CHRL_5               0x00000000      /*!< \brief 5 data bits. */
#define US_CHRL_6               0x00000040      /*!< \brief 6 data bits. */
#define US_CHRL_7               0x00000080      /*!< \brief 7 data bits. */
#define US_CHRL_8               0x000000C0      /*!< \brief 8 data bits. */

#define US_SYNC                 0x00000100      /*!< \brief Synchronous mode enable. */

#define US_PAR                  0x00000E00      /*!< \brief Parity mode mask. */
#define US_PAR_EVEN             0x00000000      /*!< \brief Even parity */
#define US_PAR_ODD              0x00000200      /*!< \brief Odd parity */
#define US_PAR_SPACE            0x00000400      /*!< \brief Space parity. */
#define US_PAR_MARK             0x00000600      /*!< \brief Marked parity. */
#define US_PAR_NO               0x00000800      /*!< \brief No parity. */
#define US_PAR_MULTIDROP        0x00000C00      /*!< \brief Multi-drop mode. */

#define US_NBSTOP               0x00003000      /*!< \brief Masks stop bit length. */
#define US_NBSTOP_1             0x00000000      /*!< \brief 1 stop bit. */
#define US_NBSTOP_1_5           0x00001000      /*!< \brief 1.5 stop bits. */
#define US_NBSTOP_2             0x00002000      /*!< \brief 2 stop bits. */

#define US_CHMODE                   0x0000C000  /*!< \brief Channel mode mask. */
#define US_CHMODE_NORMAL            0x00000000  /*!< \brief Normal mode. */
#define US_CHMODE_AUTOMATIC_ECHO    0x00004000  /*!< \brief Automatic echo. */
#define US_CHMODE_LOCAL_LOOPBACK    0x00008000  /*!< \brief Local loopback. */
#define US_CHMODE_REMOTE_LOOPBACK   0x0000C000  /*!< \brief Remote loopback. */

#define US_MODE9                0x00020000      /*!< \brief 9 bit mode. */

#define US_CLKO                 0x00040000      /*!< \brief Baud rate output enable */
/*@}*/

/*! \name Status and Interrupt Register */
/*@{*/
#define US_CSR_OFF              0x00000014      /*!< \brief USART status register offset. */
#define US0_CSR (USART0_BASE + US_CSR_OFF)      /*!< \brief Channel 0 status register address. */
#define US1_CSR (USART1_BASE + US_CSR_OFF)      /*!< \brief Channel 1 status register address. */

#define US_IER_OFF              0x00000008      /*!< \brief USART interrupt enable register offset. */
#define US0_IER (USART0_BASE + US_IER_OFF)      /*!< \brief Channel 0 interrupt enable register address. */
#define US1_IER (USART1_BASE + US_IER_OFF)      /*!< \brief Channel 1 interrupt enable register address. */

#define US_IDR_OFF              0x0000000C      /*!< \brief USART interrupt disable register offset. */
#define US0_IDR (USART0_BASE + US_IDR_OFF)      /*!< \brief Channel 0 interrupt disable register address. */
#define US1_IDR (USART1_BASE + US_IDR_OFF)      /*!< \brief Channel 1 interrupt disable register address. */