📄 i2c_m.lst
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6 unsigned char doubleE[7] = {0x88, 0x60, 0x61, 0x62, 0x63, 0x77, 0x88};
7 unsigned char idata SDATA[10];
8 unsigned char trans_done;
9 unsigned char idata Slave_Adr;
10 unsigned char idata FReceive_Done;
11 unsigned char idata FTransmitted_Done;
12 bit read;
13
14 unsigned char IrCounter = 0;
15 unsigned short IrData = 0x0000;
16 unsigned short CustomCode = 0xffff;
17 unsigned char DataCode = 0xff;
18 unsigned char Ir0Index = 0xff;
19 unsigned char Ir1Index = 0xff;
20 unsigned char IrIndex;
21
22 #define IR_LEADER_MIN 54//50
23 #define IR_LEADER_MAX 87//81
24 #define IR_LOGIC0_MIN 3
25 #define IR_LOGIC0_MAX 9// 8
26 #define IR_LOGIC1_MIN 9// 8
27 #define IR_LOGIC1_MAX 30
28
29 unsigned char wait200us = 0; //test
30 unsigned char wait20ms= 0;
31 unsigned char wait2sFlag= 0;
32
33 //------------------------------------------------------
34 //i2c interrupt service routine
35 //------------------------------------------------------
36 void i2c_isr(void) interrupt 5
37 {
38 1 switch(S1STA)
39 1 {
40 2 case Bus_error:
41 2 transreg(Bus_error);
42 2 break;
43 2
44 2 //======master transmitter mode=====
45 2 case M_START: //0x08
46 2 transreg(M_START);
47 2 S1DAT = Slave_Adr; //sla+R/W
48 2 num=0;
49 2 S1CON = RELEASE_BUS_ACK;
50 2 break;
51 2
C51 COMPILER V7.20 I2C_M 12/23/2005 17:56:11 PAGE 5
52 2 case MT_SLAVE_ACK: //0x18
53 2 transreg(MT_SLAVE_ACK);
54 2 S1DAT = doubleE[num];
55 2 num++;
56 2 S1CON = RELEASE_BUS_NONACK;
57 2 break;
58 2
59 2 case MT_DATA: //0x28
60 2 transreg(MT_DATA);
61 2 if(!read) {
62 3 if(num<7)
63 3 {
64 4 S1DAT = doubleE[num];
65 4 num++;
66 4 S1CON = RELEASE_BUS_ACK;
67 4 }
68 3 else
69 3 {
70 4 S1CON = SEND_STOP_ACK;
71 4 FTransmitted_Done=1;
72 4 }
73 3 }
74 2 else
75 2 { //ly
76 3 S1CON = SEND_START_ACK;
77 3 Slave_Adr = SLA_R;
78 3 }
79 2 break;
80 2
81 2 case MT_SLAVE_NONACK: //0x20
82 2 transreg(MT_SLAVE_NONACK);
83 2 S1CON = SEND_STOP_ACK;
84 2 break;
85 2
86 2 case MT_DATA_NONACK: //0x30
87 2 transreg(MT_DATA_NONACK);
88 2 S1CON = SEND_STOP_ACK;
89 2 break;
90 2
91 2 case M_RESTART: //0x10
92 2 transreg(M_RESTART);
93 2 S1DAT = Slave_Adr;
94 2 S1CON = RELEASE_BUS_ACK;
95 2 num = 0;
96 2 break;
97 2
98 2
99 2 //======master receiver mode================
100 2 case MR_SLAVE_ACK: //0x40
101 2 transreg(MR_SLAVE_ACK);
102 2 num=0;
103 2 S1CON = RELEASE_BUS_ACK;
104 2 break;
105 2
106 2 case MR_DATA_ACK: //0x50
107 2 transreg(MR_DATA_ACK);
108 2 SDATA[num]=S1DAT;
109 2 if(num<5)
110 2 {
111 3 S1CON = RELEASE_BUS_ACK;
112 3 transreg(SDATA[num]);
113 3 num++;
C51 COMPILER V7.20 I2C_M 12/23/2005 17:56:11 PAGE 6
114 3 }
115 2 else
116 2 {
117 3 S1CON = RELEASE_BUS_NONACK;
118 3 transreg(SDATA[num]);
119 3 num++;
120 3 }
121 2 break;
122 2
123 2 case MR_LDATA_ACK: //0x58
124 2 transreg(MR_LDATA_ACK);
125 2 S1CON=SEND_STOP_ACK;
126 2 FReceive_Done =1;
127 2 break;
128 2
129 2 case MR_SLAVE_NONACK: //0x48
130 2 transreg(MR_SLAVE_NONACK);
131 2 S1CON=SEND_STOP_ACK;
132 2 break;
133 2
134 2 //=====SLAVE RECEIVE mode===================
135 2 case SR_SLAW_ACK: //0x60
136 2 transreg(SR_SLAW_ACK);
137 2 num = 0;
138 2 S1CON=RELEASE_BUS_ACK;
139 2 break;
140 2
141 2 case SR_SLAW_NONACK: //0x68
142 2 transreg(SR_SLAW_NONACK);
143 2 num=0;
144 2 S1CON=RELEASE_BUS_NONACK;
145 2
146 2 case SR_DATA_ACK: //0x80
147 2 transreg(SR_DATA_ACK);
148 2 SDATA[num]=S1DAT;
149 2 num++;
150 2 S1CON=RELEASE_BUS_ACK;
151 2 break;
152 2
153 2 case SR_DATA_NONACK: //0x88
154 2 transreg(SR_DATA_NONACK);
155 2 SDATA[num]=S1DAT;
156 2 num++;
157 2 S1CON=RELEASE_BUS_NONACK;
158 2 break;
159 2
160 2 case SR_STOP_ACK: //0xA0 receive has done
161 2 transreg(SR_STOP_ACK);
162 2 S1CON=RELEASE_BUS_ACK;
163 2 FReceive_Done = 1;
164 2 break;
165 2
166 2 //=====SLAVE TRANSMITTER mode===============
167 2 case ST_SLAR_ACK: //0xA8
168 2 transreg(ST_SLAR_ACK);
169 2 num=0;
170 2 S1DAT = DATA[num];
171 2 num++;
172 2 S1CON=RELEASE_BUS_ACK;
173 2 break;
174 2
175 2 case ST_DATA_ACK: //0xB8
C51 COMPILER V7.20 I2C_M 12/23/2005 17:56:11 PAGE 7
176 2 transreg(ST_DATA_ACK);
177 2 S1DAT=DATA[num];
178 2 num++;
179 2 S1CON = RELEASE_BUS_ACK;
180 2
181 2 break;
182 2
183 2 case ST_STOP_NONACK : //0xC0
184 2 transreg(ST_STOP_NONACK);
185 2 S1CON=RELEASE_BUS_ACK;
186 2 FTransmitted_Done =1;
187 2 break;
188 2
189 2 default:
190 2 transreg(0xFF);
191 2 break;
192 2 }
193 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 419 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = 27 ----
IDATA SIZE = 13 ----
BIT SIZE = 1 ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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