📄 main_m.lst
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C51 COMPILER V7.20 MAIN_M 12/23/2005 17:56:49 PAGE 1
C51 COMPILER V7.20, COMPILATION OF MODULE MAIN_M
OBJECT MODULE PLACED IN main_m.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE main_m.c BROWSE DEBUG OBJECTEXTEND LISTINCLUDE
line level source
1 #include <intrins.h>
1 =1 /*--------------------------------------------------------------------------
2 =1 INTRINS.H
3 =1
4 =1 Intrinsic functions for C51.
5 =1 Copyright (c) 1988-2004 Keil Elektronik GmbH and Keil Software, Inc.
6 =1 All rights reserved.
7 =1 --------------------------------------------------------------------------*/
8 =1
9 =1 #ifndef __INTRINS_H__
10 =1 #define __INTRINS_H__
11 =1
12 =1 extern void _nop_ (void);
13 =1 extern bit _testbit_ (bit);
14 =1 extern unsigned char _cror_ (unsigned char, unsigned char);
15 =1 extern unsigned int _iror_ (unsigned int, unsigned char);
16 =1 extern unsigned long _lror_ (unsigned long, unsigned char);
17 =1 extern unsigned char _crol_ (unsigned char, unsigned char);
18 =1 extern unsigned int _irol_ (unsigned int, unsigned char);
19 =1 extern unsigned long _lrol_ (unsigned long, unsigned char);
20 =1 extern unsigned char _chkfloat_(float);
21 =1 extern void _push_ (unsigned char _sfr);
22 =1 extern void _pop_ (unsigned char _sfr);
23 =1
24 =1 #endif
25 =1
2 #include"3552.h"
1 =1 /*--------------------------------------------------------------------------
2 =1 REG52.H
3 =1
4 =1 Header file for generic 80C52 and 80C32 microcontroller.
5 =1 Copyright (c) 1988-2001 Keil Elektronik GmbH and Keil Software, Inc.
6 =1 All rights reserved.
7 =1 --------------------------------------------------------------------------*/
8 =1
9 =1 /* BYTE Registers */
10 =1 sfr P0 = 0x80;
11 =1 sfr P1 = 0x90;
12 =1 sfr P2 = 0xA0;
13 =1 sfr P3 = 0xB0;
14 =1 sfr P4 = 0xC0; //ly
15 =1 sfr PSW = 0xD0;
16 =1 sfr ACC = 0xE0;
17 =1 sfr A = 0xE0;
18 =1 sfr B = 0xF0;
19 =1 sfr SP = 0x81; //stack pointer
20 =1 sfr DPL = 0x82;
21 =1 sfr DPH = 0x83;
22 =1 sfr PCON = 0x87;
23 =1 sfr TCON = 0x88;
24 =1 sfr TMOD = 0x89;
25 =1 sfr TL0 = 0x8A;
26 =1 sfr TL1 = 0x8B;
27 =1 sfr TH0 = 0x8C;
28 =1 sfr TH1 = 0x8D;
C51 COMPILER V7.20 MAIN_M 12/23/2005 17:56:49 PAGE 2
29 =1 sfr IE = 0xA8;
30 =1 sfr IP = 0xB8;
31 =1 sfr SCON = 0x98;
32 =1 sfr SBUF = 0x99;
33 =1
34 =1 //ly
35 =1 sfr PDCON = 0xF8;
36 =1 sfr AUXR1 = 0xA2;
37 =1
38 =1 /* 8052 Extensions */
39 =1 sfr T2CON = 0xC8;
40 =1 sfr RCAP2L = 0xCA;
41 =1 sfr RCAP2H = 0xCB;
42 =1 sfr TL2 = 0xCC;
43 =1 sfr TH2 = 0xCD;
44 =1
45 =1 sfr S1CON = 0xD8; //I2C control
46 =1 sfr S1STA = 0xD9;
47 =1 sfr S1DAT = 0xDA;
48 =1 sfr S1ADR = 0xDB;
49 =1 /* BIT Registers */
50 =1 /* PSW */
51 =1 sbit CY = PSW^7;
52 =1 sbit AC = PSW^6;
53 =1 sbit F0 = PSW^5;
54 =1 sbit RS1 = PSW^4;
55 =1 sbit RS0 = PSW^3;
56 =1 sbit OV = PSW^2;
57 =1 sbit P = PSW^0; //8052 only
58 =1
59 =1 /* TCON */
60 =1 sbit TF1 = TCON^7;
61 =1 sbit TR1 = TCON^6;
62 =1 sbit TF0 = TCON^5;
63 =1 sbit TR0 = TCON^4;
64 =1 sbit IE1 = TCON^3;
65 =1 sbit IT1 = TCON^2;
66 =1 sbit IE0 = TCON^1;
67 =1 sbit IT0 = TCON^0;
68 =1
69 =1 /* IE */
70 =1 sbit EA = IE^7;
71 =1 sbit ET2 = IE^6;
72 =1 sbit ES1 = IE^5; //Enable I2C interrupt
73 =1 sbit ES = IE^4;
74 =1 sbit ET1 = IE^3;
75 =1 sbit EX1 = IE^2;
76 =1 sbit ET0 = IE^1;
77 =1 sbit EX0 = IE^0;
78 =1
79 =1 /* IP */
80 =1 sbit PT2 = IP^5;
81 =1 sbit PS = IP^4;
82 =1 sbit PT1 = IP^3;
83 =1 sbit PX1 = IP^2;
84 =1 sbit PT0 = IP^1;
85 =1 sbit PX0 = IP^0;
86 =1
87 =1 /* P0 */
88 =1 sbit relay_on = P0^6;
89 =1
90 =1 /* P1 */
C51 COMPILER V7.20 MAIN_M 12/23/2005 17:56:49 PAGE 3
91 =1 sbit VS_ON = P1^0;
92 =1 sbit VD_5 = P1^1;
93 =1 sbit RLY_ON = P1^2;
94 =1 sbit P1_3 = P1^3;
95 =1 sbit P1_4 = P1^4;
96 =1
97 =1 /* P3 */
98 =1 sbit TVP9000Reset = P3^7; //TVP9000 reset pin, low active
99 =1 sbit WR = P3^6;
100 =1 sbit PowerSwitch = P3^5;
101 =1 sbit T0 = P3^4;
102 =1 sbit INT1 = P3^3;
103 =1 sbit INT0 = P3^2;
104 =1 sbit TXD = P3^1;
105 =1 sbit RXD = P3^0;
106 =1
107 =1 /* P4 */
108 =1 sbit ACD = P4^2; //ACD detect
109 =1
110 =1 /* SCON */
111 =1 sbit SM0 = SCON^7;
112 =1 sbit SM1 = SCON^6;
113 =1 sbit SM2 = SCON^5;
114 =1 sbit REN = SCON^4;
115 =1 sbit TB8 = SCON^3;
116 =1 sbit RB8 = SCON^2;
117 =1 sbit TI = SCON^1;
118 =1 sbit RI = SCON^0;
119 =1
120 =1 /* P1 */
121 =1 sbit T2EX = P1^1; // 8052 only
122 =1 sbit T2 = P1^0; // 8052 only
123 =1
124 =1 /* T2CON */
125 =1 sbit TF2 = T2CON^7;
126 =1 sbit EXF2 = T2CON^6;
127 =1 sbit RCLK = T2CON^5;
128 =1 sbit TCLK = T2CON^4;
129 =1 sbit EXEN2 = T2CON^3;
130 =1 sbit TR2 = T2CON^2;
131 =1 sbit C_T2 = T2CON^1;
132 =1 sbit CP_RL2 = T2CON^0;
133 =1 /*S1CON*/
134 =1
135 =1 sbit CR7 = S1CON^7;
136 =1 sbit ENS1 = S1CON^6;
137 =1 sbit STA = S1CON^5;
138 =1 sbit STO = S1CON^4;
139 =1 sbit SI = S1CON^3;
140 =1 sbit AA = S1CON^2;
141 =1 sbit CR1 = S1CON^1;
142 =1 sbit CR0 = S1CON^0;
3 #include "i2cm.h"
1 =1 #ifndef _i2cm_H
2 =1 #define _i2cm_H
3 =1
4 =1
5 =1 void i2c_isr(void);
6 =1 void transc (char c);
7 =1 void transreg(char c);
8 =1 int hextoascii(int hex2);
9 =1 void transs(char *s);
C51 COMPILER V7.20 MAIN_M 12/23/2005 17:56:49 PAGE 4
10 =1 void Initial();
11 =1
12 =1 #define SLA_R 0xA1;
13 =1 #define SLA_W 0xA0;
14 =1
15 =1 #define Bus_error 0x00 //
16 =1 #define M_START 0x08 //master send start
17 =1 #define MT_SLAVE_ACK 0x18 //master transmitter mode for slave_write ACK
18 =1 #define MT_DATA 0x28 //master transmitter mode for transmit data
19 =1 #define MT_SLAVE_NONACK 0x20 //master transmitter mode for slave_write NONACK
20 =1 #define MT_DATA_NONACK 0x30 //master transmitter mode for transmit data NONACK
21 =1 #define M_RESTART 0x10 //master send re_start
22 =1
23 =1 #define MR_SLAVE_ACK 0x40 //master receive mode for slave_read ACK
24 =1 #define MR_DATA_ACK 0x50 //master receive mode for receive data
25 =1 #define MR_LDATA_ACK 0x58 //master receive mode for receive last data
26 =1 #define MR_SLAVE_NONACK 0x48 //master receive mode for slave_read NONACK
27 =1
28 =1 #define SR_SLAW_ACK 0x60 //slave receive,receive slave address has done
29 =1 #define SR_SLAW_NONACK 0x68 //slave receive,return nonack
30 =1 #define SR_DATA_ACK 0x80 //slave receive,receive data has done
31 =1 #define SR_DATA_NONACK 0x88 //slave receive,receive data has done and nonsck
32 =1 #define SR_STOP_ACK 0xA0 //slave receive,receive stop or start
33 =1
34 =1 #define ST_SLAR_ACK 0xA8 //then send data
35 =1 #define ST_DATA_ACK 0xB8 //then send data
36 =1 #define ST_STOP_NONACK 0xC0
37 =1
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