i2c_m.c

8051模拟IIC总线读写24CXX原程序。

#include "3552.h"
#include "i2cm.h"

unsigned char num = 0x00;
unsigned char DATA[6] ={0x3,0x4};
unsigned char doubleE[7] = {0x88, 0x60, 0x61, 0x62, 0x63, 0x77, 0x88};
unsigned char idata SDATA[10];
unsigned char trans_done;
unsigned char idata Slave_Adr;
unsigned char idata FReceive_Done;
unsigned char idata FTransmitted_Done;
bit read;

unsigned char IrCounter = 0;
unsigned short IrData = 0x0000;
unsigned short CustomCode = 0xffff;
unsigned char DataCode = 0xff;
unsigned char Ir0Index = 0xff;
unsigned char Ir1Index = 0xff;
unsigned char IrIndex;

#define IR_LEADER_MIN	54//50
#define IR_LEADER_MAX	87//81
#define IR_LOGIC0_MIN	3
#define IR_LOGIC0_MAX	9//	8
#define IR_LOGIC1_MIN	9//	8
#define IR_LOGIC1_MAX	30

unsigned char wait200us = 0;		//test
unsigned char wait20ms= 0;
unsigned char wait2sFlag= 0;

//------------------------------------------------------
//i2c interrupt service routine
//------------------------------------------------------
void i2c_isr(void) interrupt 5
{
    switch(S1STA)
	{
		case Bus_error:
        		transreg(Bus_error);
	       break;
		   
        //======master  transmitter mode=====
   		case M_START:				//0x08		
        		transreg(M_START);        
        		S1DAT = Slave_Adr;	 		//sla+R/W	
			num=0;
        		S1CON = RELEASE_BUS_ACK;    
		break;

		case MT_SLAVE_ACK:  		 //0x18
        		transreg(MT_SLAVE_ACK);
			S1DAT = doubleE[num]; 
       		num++;
			S1CON = RELEASE_BUS_NONACK;
		break;

		case MT_DATA:				//0x28
 	    		transreg(MT_DATA);
			if(!read) {
        			if(num<7)
				{ 
					S1DAT = doubleE[num];
					num++;
					S1CON = RELEASE_BUS_ACK;
				}
				else
				{
				 	S1CON = SEND_STOP_ACK;
					FTransmitted_Done=1;
				}		
			}
			else 
			{	//ly
				S1CON = SEND_START_ACK;
				Slave_Adr = SLA_R;
			}
	    	break;
			
		case MT_SLAVE_NONACK:		//0x20
			transreg(MT_SLAVE_NONACK);
			S1CON = SEND_STOP_ACK;
		break;

		case MT_DATA_NONACK:		//0x30
		transreg(MT_DATA_NONACK);
		S1CON = SEND_STOP_ACK;		
		break;

		case M_RESTART:				//0x10
		transreg(M_RESTART);
		S1DAT = Slave_Adr;
        	S1CON = RELEASE_BUS_ACK; 
		num = 0;
		break;


		//======master receiver mode================
		case MR_SLAVE_ACK:			//0x40
		transreg(MR_SLAVE_ACK);
		num=0;
		S1CON = RELEASE_BUS_ACK;    
		break;

		case MR_DATA_ACK:		    //0x50	
			transreg(MR_DATA_ACK);	
	       	SDATA[num]=S1DAT;	
			if(num<5)
			{			
        			S1CON = RELEASE_BUS_ACK;	
				transreg(SDATA[num]);
				num++;		
  			}
	      		else
			{
				S1CON = RELEASE_BUS_NONACK; 
				transreg(SDATA[num]);
				num++;
			}
		break;

		case MR_LDATA_ACK:			//0x58
			transreg(MR_LDATA_ACK);
        		S1CON=SEND_STOP_ACK;
			FReceive_Done =1;
		break;

		case MR_SLAVE_NONACK:		//0x48
		transreg(MR_SLAVE_NONACK);
		S1CON=SEND_STOP_ACK;
		break;

		//=====SLAVE RECEIVE mode===================
		case SR_SLAW_ACK:			//0x60
		transreg(SR_SLAW_ACK);
		num = 0;
		S1CON=RELEASE_BUS_ACK;
		break;

		case SR_SLAW_NONACK:		//0x68
		transreg(SR_SLAW_NONACK);
		num=0;
		S1CON=RELEASE_BUS_NONACK;

		case SR_DATA_ACK:			//0x80
		transreg(SR_DATA_ACK);
		SDATA[num]=S1DAT;
		num++;
		S1CON=RELEASE_BUS_ACK;
		break;

		case SR_DATA_NONACK:		//0x88		
		transreg(SR_DATA_NONACK);
		SDATA[num]=S1DAT;
		num++;
		S1CON=RELEASE_BUS_NONACK;
		break;

		case SR_STOP_ACK:			//0xA0	receive has done
		transreg(SR_STOP_ACK);	
		S1CON=RELEASE_BUS_ACK;
		FReceive_Done = 1;
		break;

		//=====SLAVE TRANSMITTER mode===============
		case ST_SLAR_ACK:			//0xA8
		transreg(ST_SLAR_ACK);
		num=0;
		S1DAT = DATA[num]; 
        num++;
		S1CON=RELEASE_BUS_ACK;
		break;

		case ST_DATA_ACK:			//0xB8
		transreg(ST_DATA_ACK);	
 		S1DAT=DATA[num];
		num++;
		S1CON = RELEASE_BUS_ACK;

		break;

		case ST_STOP_NONACK	:		//0xC0
		transreg(ST_STOP_NONACK);
		S1CON=RELEASE_BUS_ACK;
		FTransmitted_Done =1;
		break;

		default:
			transreg(0xFF);
		break;
	}
}