📄 pdc4000.h
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/******************************************************************************
* File Name:
* PDC4000.h
* Description:
* The header file for the CanCard's Windows WDM driver.
* Revision History:
* 02-28-02 : PDC4000 1.00
******************************************************************************/
#ifdef __cplusplus
extern "C"
{
#endif
#include <wdm.h>
#ifdef __cplusplus
}
#endif
#include "GUIDs.h"
#define DBG_NAME "PDC4000: "
//The max count of the scatter/gather element.
#define SGE_MAX_COUNT 8
#define CFG_VENDOR_ID 0x000
#define CFG_COMMAND 0x004
#define CFG_REV_ID 0x008
#define CFG_CACHE_SIZE 0x00C
#define CFG_BAR0 0x010
#define CFG_BAR1 0x014
#define CFG_BAR2 0x018
#define CFG_BAR3 0x01C
#define CFG_BAR4 0x020
#define CFG_BAR5 0x024
#define CFG_CIS_PTR 0x028
#define CFG_SUB_VENDOR_ID 0x02C
#define CFG_EXP_ROM_BASE 0x030
#define CFG_CAP_PTR 0x034
#define CFG_RESERVED1 0x038
#define CFG_INT_LINE 0x03C
/* PCI Configuration Registers */
#define PCI9054_VENDOR_ID CFG_VENDOR_ID
#define PCI9054_COMMAND CFG_COMMAND
#define PCI9054_REV_ID CFG_REV_ID
#define PCI9054_CACHE_SIZE CFG_CACHE_SIZE
#define PCI9054_RTR_BASE CFG_BAR0
#define PCI9054_RTR_IO_BASE CFG_BAR1
#define PCI9054_LOCAL_BASE0 CFG_BAR2
#define PCI9054_LOCAL_BASE1 CFG_BAR3
#define PCI9054_UNUSED_BASE1 CFG_BAR4
#define PCI9054_UNUSED_BASE2 CFG_BAR5
#define PCI9054_CIS_PTR CFG_CIS_PTR
#define PCI9054_SUB_ID CFG_SUB_VENDOR_ID
#define PCI9054_EXP_ROM_BASE CFG_EXP_ROM_BASE
#define PCI9054_CAP_PTR CFG_CAP_PTR
#define PCI9054_RESERVED2 CFG_RESERVED1
#define PCI9054_INT_LINE CFG_INT_LINE
#define PCI9054_PM_CAP_ID 0x040
#define PCI9054_PM_CSR 0x044
#define PCI9054_HS_CAP_ID 0x048
#define PCI9054_VPD_CAP_ID 0x04C
#define PCI9054_VPD_DATA 0x050
//9054 Registers Address
#define PCI9054_REG_BASE 0x000
/* Local Configuration Registers */
#define PCI9054_SPACE0_RANGE (PCI9054_REG_BASE + 0x000)
#define PCI9054_SPACE0_REMAP (PCI9054_REG_BASE + 0x004)
#define PCI9054_MODE_DMA_ARBITRATION (PCI9054_REG_BASE + 0x008) //
#define PCI9054_ENDIAN_DESC (PCI9054_REG_BASE + 0x00C)
#define PCI9054_EXP_ROM_RANGE (PCI9054_REG_BASE + 0x010)
#define PCI9054_EXP_ROM_REMAP (PCI9054_REG_BASE + 0x014)
#define PCI9054_SPACE0_ROM_DESC (PCI9054_REG_BASE + 0x018)
#define PCI9054_DM_RANGE (PCI9054_REG_BASE + 0x01C)
#define PCI9054_DM_MEM_BASE (PCI9054_REG_BASE + 0x020)
#define PCI9054_DM_IO_BASE (PCI9054_REG_BASE + 0x024)
#define PCI9054_DM_PCI_MEM_REMAP (PCI9054_REG_BASE + 0x028)
#define PCI9054_DM_PCI_IO_CONFIG (PCI9054_REG_BASE + 0x02C)
#define PCI9054_SPACE1_RANGE (PCI9054_REG_BASE + 0x0F0)
#define PCI9054_SPACE1_REMAP (PCI9054_REG_BASE + 0x0F4)
#define PCI9054_SPACE1_DESC (PCI9054_REG_BASE + 0x0F8)
#define PCI9054_DM_DAC (PCI9054_REG_BASE + 0x0FC)
/* Runtime Registers */
#define PCI9054_MAILBOX0 0x078
#define PCI9054_MAILBOX1 0x07C
#define PCI9054_MAILBOX2 (PCI9054_REG_BASE + 0x048)
#define PCI9054_MAILBOX3 (PCI9054_REG_BASE + 0x04C)
#define PCI9054_MAILBOX4 (PCI9054_REG_BASE + 0x050)
#define PCI9054_MAILBOX5 (PCI9054_REG_BASE + 0x054)
#define PCI9054_MAILBOX6 (PCI9054_REG_BASE + 0x058)
#define PCI9054_MAILBOX7 (PCI9054_REG_BASE + 0x05C)
#define PCI9054_LOCAL_DOORBELL (PCI9054_REG_BASE + 0x060)
#define PCI9054_PCI_DOORBELL (PCI9054_REG_BASE + 0x064)
#define PCI9054_INT_CTRL_STAT (PCI9054_REG_BASE + 0x068)
#define PCI9054_EEPROM_CTRL_STAT (PCI9054_REG_BASE + 0x06C)
#define PCI9054_PERM_VENDOR_ID (PCI9054_REG_BASE + 0x070)
#define PCI9054_REVISION_ID (PCI9054_REG_BASE + 0x074)
/* DMA Registers */
#define PCI9054_DMA0_MODE (PCI9054_REG_BASE + 0x080)
#define PCI9054_DMA0_PCI_ADDR (PCI9054_REG_BASE + 0x084)
#define PCI9054_DMA0_LOCAL_ADDR (PCI9054_REG_BASE + 0x088)
#define PCI9054_DMA0_COUNT (PCI9054_REG_BASE + 0x08C)
#define PCI9054_DMA0_DESC_PTR (PCI9054_REG_BASE + 0x090)
#define PCI9054_DMA1_MODE (PCI9054_REG_BASE + 0x094)
#define PCI9054_DMA1_PCI_ADDR (PCI9054_REG_BASE + 0x098)
#define PCI9054_DMA1_LOCAL_ADDR (PCI9054_REG_BASE + 0x09C)
#define PCI9054_DMA1_COUNT (PCI9054_REG_BASE + 0x0A0)
#define PCI9054_DMA1_DESC_PTR (PCI9054_REG_BASE + 0x0A4)
#define PCI9054_DMA_COMMAND_STAT (PCI9054_REG_BASE + 0x0A8)
#define PCI9054_DMA_ARBIT (PCI9054_REG_BASE + 0x0AC)
#define PCI9054_DMA_THRESHOLD (PCI9054_REG_BASE + 0x0B0)
#define PCI9054_DMA0_PCI_DAC (PCI9054_REG_BASE + 0x0B4)
#define PCI9054_DMA1_PCI_DAC (PCI9054_REG_BASE + 0x0B8)
/* Messaging Unit Registers */
#define PCI9054_OUTPOST_INT_STAT (PCI9054_REG_BASE + 0x030)
#define PCI9054_OUTPOST_INT_MASK (PCI9054_REG_BASE + 0x034)
#define PCI9054_MU_CONFIG (PCI9054_REG_BASE + 0x0C0)
#define PCI9054_FIFO_BASE_ADDR (PCI9054_REG_BASE + 0x0C4)
#define PCI9054_INFREE_HEAD_PTR (PCI9054_REG_BASE + 0x0C8)
#define PCI9054_INFREE_TAIL_PTR (PCI9054_REG_BASE + 0x0CC)
#define PCI9054_INPOST_HEAD_PTR (PCI9054_REG_BASE + 0x0D0)
#define PCI9054_INPOST_TAIL_PTR (PCI9054_REG_BASE + 0x0D4)
#define PCI9054_OUTFREE_HEAD_PTR (PCI9054_REG_BASE + 0x0D8)
#define PCI9054_OUTFREE_TAIL_PTR (PCI9054_REG_BASE + 0x0DC)
#define PCI9054_OUTPOST_HEAD_PTR (PCI9054_REG_BASE + 0x0E0)
#define PCI9054_OUTPOST_TAIL_PTR (PCI9054_REG_BASE + 0x0E4)
#define PCI9054_FIFO_CTRL_STAT (PCI9054_REG_BASE + 0x0E8)
/* Additional register defintions */
#define MAX_PCI9054_REG_OFFSET (PCI9054_REG_BASE + 0x100)
#define PCI9054_IN_FIFO_PORT 0x040
#define PCI9054_OUT_FIFO_PORT 0x044
typedef struct _REG_DATA
{
ULONG lRegAddress;
ULONG lBitsToSet;
ULONG lBitsToClear;
}REG_DATA, * PREG_DATA;
//DMA Defines
#define NUMBER_OF_DMA_CHANNELS 2
#define MAX_DMA_LENGTH 0x10000
/* DMA Command Definitions */
typedef enum _DMA_COMMAND
{
DMA_START,
DMA_PAUSE,
DMA_RESUME,
DMA_ABORT,
DMA_STATUS
} DMA_COMMAND, *PDMA_COMMAND;
/* Various DMA states */
typedef enum _DMA_STATE
{
DMA_STATE_CLOSED = 0,
DMA_STATE_BLOCK,
DMA_STATE_SGL,
DMA_STATE_SHUTTLE,
} DMA_STATE;
/* DMA Channel Priority Definitions */
typedef enum _DMA_CHANNEL_PRIORITY
{
Channel0Highest,
Channel1Highest,
Channel2Highest,
Channel3Highest,
Rotational
} DMA_CHANNEL_PRIORITY;
//Return Code Values
typedef enum _RETURN_CODE
{
RC_SUCCESS = 0,
RC_FAILED,
RC_ACCESSDENIED,
RC_DMA_CHANNEL_UNAVAILABLE,
RC_DMA_CHANNEL_INVALID,
RC_DMA_CHANNEL_TYPE_ERROR,
RC_DMA_IN_PROGRESS,
RC_DMA_DONE,
RC_DMA_PAUSED,
RC_DMA_NOT_PAUSED,
RC_DMA_COMMAND_INVALID,
RC_DMA_MAN_READY,
RC_DMA_MAN_NOT_READY,
RC_DMA_INVALID_CHANNEL_PRIORITY,
RC_DMA_MAN_CORRUPTED,
RC_DMA_INVALID_ELEMENT_INDEX,
RC_DMA_NO_MORE_ELEMENTS,
RC_DMA_SGL_INVALID,
RC_DMA_SGL_QUEUE_FULL,
RC_NULL_PARAMETER,
RC_INVALID_BUS_INDEX,
RC_UNSUPPORT_FUNCITON,
RC_INVALID_PCI_SPACE,
RC_INVALID_LOCAL_SPACE,
RC_INVALID_SIZE,
RC_INVALID_ADDRESS,
RC_INVALID_ACCESS_TYPE,
RC_INVALID_INDEX,
RC_MU_NOT_READY,
RC_MU_FIFO_EMPTY,
RC_MU_FIFO_FULL,
RC_INVALID_REGISTER,
RC_DOOR_BELL_CLEAR_FAILED,
RC_INVALID_USER_PIN,
RC_INVALID_USER_STATE,
RC_EEPROM_NOT_PRESENT,
RC_EEPROM_TYPE_NOT_SUPPORTED,
RC_EEPROM_BLANK,
RC_CONFIG_ACCESS_FAILED,
RC_INVALID_DEVICE_INFO,
RC_NO_ACTIVE_DRIVER,
RC_INSUFFICIENTRESOURCES,
RC_OBJECT_ALREADY_ALLOCATED,
RC_ALEEADY_INITIALIZED,
RC_NOT_INITIALIZED,
RC_BAD_CONFIG_REG_ENDIAN_MODE,
RC_INVALID_POWER_STATE,
RC_POWER_DOWN,
RC_FLYBY_NOT_SUPPORTED,
RC_NOT_SUPPORT_THIS_CHANNEL,
RC_NO_ACTION,
RC_HS_NOT_SUPPORTED,
RC_VPD_NOT_SUPPORTED,
RC_VPD_NOT_ENABLED,
RC_NO_MORE_CAP,
RC_INVALID_OFFSET,
RC_BAD_PIN_DIRECTION,
RC_PCI_TIMEOUT,
RC_DMA_CHANNEL_CLOSED,
RC_DMA_CHANNEL_ERROR,
RC_INVALID_HANDLE,
RC_BUFFER_NOT_READY,
RC_INVALID_DATA,
RC_DO_NOTHING,
RC_DMA_SGL_BUILD_FAILED,
RC_PM_NOT_SUPPORTED,
RC_LAST_ERROR /* do not add API errors below this line */
} RETURN_CODE, *PRETURN_CODE;
typedef struct _PCI9054_SCATTER_GATHER_ELEMENT
{
ULONG lPciLowAddress;
ULONG lLocalAddress;
ULONG lLength;
ULONG lNextDescriptorPointer;
#ifdef PCI_DAC
ULONG lPciHighAddress;
#endif
}PCI9054_SCATTER_GATHER_ELEMENT, *PPCI9054_SCATTER_GATHER_ELEMENT;
/* DMA Transfer Element Union Structure */
typedef struct _DMA_TRANSFER_ELEMENT
{
ULONG lPciAddress; //PCI Address
ULONG lPciDualAddress; //PCI Dual cycle address
ULONG lLocalAddress; //Local Address
ULONG lTransferSize; //Transfer Size
//DMA Channel Descriptor Pointer;
ULONG DescriptorLocation :1; //对应DMA Channel X Descriptor Pointer：Descriptor Location位
ULONG EndOfChain :1; //对应DMA Channel X Descriptor Pointer：End of Chain位
ULONG InterruptAfterTerminalCount :1; //对应DMA Channel X Descriptor Pointer：Interrupt After TerminalCount位
ULONG DirectionOfTransfer :1; //对应DMA Channel X Descriptor Pointer：Direction Of Transfer位
ULONG NextDescriptorAddress :28;//对应DMA Channel X Descriptor Pointer：Next Descriptor Address位
/*
* The DMA Transfer Element must always start on a 16 byte
* boundary so the following reserve field ensures this. Total size = 0x30.
*/
ULONG lReserved[12];
} DMA_TRANSFER_ELEMENT, *PDMA_TRANSFER_ELEMENT;
/* DMA Channel Descriptor Structure */
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