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Reduced&nbsp;Instruction&nbsp;Set&nbsp;Computer.&nbsp;Describes&nbsp;the&nbsp;architecture&nbsp;of&nbsp;a&nbsp;processor&nbsp;<br />
family.&nbsp;RISC&nbsp;processors&nbsp;generally&nbsp;feature&nbsp;fixed-length&nbsp;instructions,&nbsp;a&nbsp;load-&nbsp;<br />
store&nbsp;<br />
memory&nbsp;architecture,&nbsp;and&nbsp;a&nbsp;large&nbsp;number&nbsp;of&nbsp;general-purpose&nbsp;registers&nbsp;and/or&nbsp;<br />
register&nbsp;windows.&nbsp;The&nbsp;MIPS&nbsp;processor&nbsp;family&nbsp;is&nbsp;an&nbsp;excellent&nbsp;example.&nbsp;Contras&nbsp;<br />
t&nbsp;<br />
with&nbsp;CISC.&nbsp;<br />
ROM&nbsp;<br />
Read-Only&nbsp;Memory.&nbsp;A&nbsp;broad&nbsp;classification&nbsp;of&nbsp;memory&nbsp;devices&nbsp;that&nbsp;includes&nbsp;all&nbsp;<br />
&nbsp;<br />
devices&nbsp;in&nbsp;which&nbsp;the&nbsp;individual&nbsp;memory&nbsp;locations&nbsp;may&nbsp;be&nbsp;read,&nbsp;but&nbsp;not&nbsp;writte&nbsp;<br />
n.&nbsp;<br />
ROM&nbsp;emulator&nbsp;<br />
A&nbsp;debugging&nbsp;tool&nbsp;that&nbsp;takes&nbsp;the&nbsp;place&nbsp;of-or&nbsp;emulates-the&nbsp;ROM&nbsp;on&nbsp;your&nbsp;target&nbsp;<br />
board.&nbsp;A&nbsp;ROM&nbsp;emulator&nbsp;acts&nbsp;very&nbsp;much&nbsp;like&nbsp;a&nbsp;debug&nbsp;monitor,&nbsp;except&nbsp;that&nbsp;it&nbsp;<br />
includes&nbsp;its&nbsp;own&nbsp;serial&nbsp;or&nbsp;network&nbsp;connection&nbsp;to&nbsp;the&nbsp;host.&nbsp;<br />
ROM&nbsp;monitor&nbsp;<br />
See&nbsp;debug&nbsp;monitor.&nbsp;<br />
RTOS&nbsp;<br />
Real-Time&nbsp;Operating&nbsp;System.&nbsp;An&nbsp;operating&nbsp;system&nbsp;designed&nbsp;specifically&nbsp;for&nbsp;us&nbsp;<br />
e&nbsp;in&nbsp;<br />
real-time&nbsp;systems.&nbsp;<br />
race&nbsp;condition&nbsp;<br />
A&nbsp;situation&nbsp;in&nbsp;which&nbsp;the&nbsp;outcome&nbsp;of&nbsp;a&nbsp;program&nbsp;may&nbsp;be&nbsp;affected&nbsp;by&nbsp;the&nbsp;exact&nbsp;o&nbsp;<br />
rder&nbsp;<br />
in&nbsp;which&nbsp;the&nbsp;instructions&nbsp;are&nbsp;executed.&nbsp;Race&nbsp;conditions&nbsp;are&nbsp;only&nbsp;an&nbsp;issue&nbsp;wh&nbsp;<br />
ere&nbsp;<br />
interrupts&nbsp;and/or&nbsp;preemption&nbsp;are&nbsp;possible&nbsp;and&nbsp;where&nbsp;critical&nbsp;sections&nbsp;exist.&nbsp;<br />
&nbsp;<br />
real-time&nbsp;system&nbsp;<br />
Any&nbsp;computer&nbsp;system,&nbsp;embedded&nbsp;or&nbsp;otherwise,&nbsp;that&nbsp;has&nbsp;deadlines.&nbsp;The&nbsp;followin&nbsp;<br />
g&nbsp;<br />
question&nbsp;can&nbsp;be&nbsp;used&nbsp;to&nbsp;distinguish&nbsp;real-time&nbsp;systems&nbsp;from&nbsp;the&nbsp;rest:&nbsp;&quot;Is&nbsp;a&nbsp;l&nbsp;<br />
ate&nbsp;<br />
answer&nbsp;as&nbsp;bad,&nbsp;or&nbsp;even&nbsp;worse,&nbsp;than&nbsp;a&nbsp;wrong&nbsp;answer?&quot;&nbsp;In&nbsp;other&nbsp;words,&nbsp;what&nbsp;hap&nbsp;<br />
pens&nbsp;<br />
if&nbsp;the&nbsp;computation&nbsp;doesn't&nbsp;finish&nbsp;in&nbsp;time?&nbsp;If&nbsp;nothing&nbsp;bad&nbsp;happens,&nbsp;it's&nbsp;not&nbsp;&nbsp;<br />
a&nbsp;<br />
real-time&nbsp;system.&nbsp;If&nbsp;someone&nbsp;dies&nbsp;or&nbsp;the&nbsp;mission&nbsp;fails,&nbsp;it's&nbsp;generally&nbsp;consi&nbsp;<br />
dered&nbsp;<br />
&quot;hard&quot;&nbsp;real-time,&nbsp;which&nbsp;is&nbsp;meant&nbsp;to&nbsp;imply&nbsp;that&nbsp;the&nbsp;system&nbsp;has&nbsp;&quot;hard&quot;&nbsp;deadlin&nbsp;<br />
es.&nbsp;<br />
Everything&nbsp;in&nbsp;between&nbsp;is&nbsp;&quot;soft&quot;&nbsp;real-time.&nbsp;<br />
recursive&nbsp;<br />
Said&nbsp;of&nbsp;software&nbsp;that&nbsp;calls&nbsp;itself.&nbsp;Recursion&nbsp;should&nbsp;generally&nbsp;be&nbsp;avoided&nbsp;in&nbsp;<br />
&nbsp;an&nbsp;<br />
embedded&nbsp;system,&nbsp;since&nbsp;it&nbsp;frequently&nbsp;requires&nbsp;a&nbsp;large&nbsp;stack.&nbsp;<br />
reentrant&nbsp;<br />
Said&nbsp;of&nbsp;software&nbsp;that&nbsp;can&nbsp;be&nbsp;executed&nbsp;multiple&nbsp;times&nbsp;simultaneously.&nbsp;A&nbsp;reent&nbsp;<br />
rant&nbsp;<br />
function&nbsp;can&nbsp;be&nbsp;safely&nbsp;called&nbsp;recursively&nbsp;or&nbsp;from&nbsp;multiple&nbsp;tasks.&nbsp;The&nbsp;key&nbsp;to&nbsp;<br />
&nbsp;making&nbsp;<br />
code&nbsp;reentrant&nbsp;is&nbsp;to&nbsp;ensure&nbsp;mutual&nbsp;exclusion&nbsp;whenever&nbsp;accessing&nbsp;global&nbsp;varia&nbsp;<br />
bles&nbsp;<br />
or&nbsp;shared&nbsp;registers.&nbsp;<br />
register&nbsp;<br />
A&nbsp;memory&nbsp;location&nbsp;that&nbsp;is&nbsp;part&nbsp;of&nbsp;a&nbsp;processor&nbsp;or&nbsp;an&nbsp;I/O&nbsp;device.&nbsp;In&nbsp;other&nbsp;wor&nbsp;<br />
ds,&nbsp;<br />
it's&nbsp;not&nbsp;normal&nbsp;memory.&nbsp;Generally,&nbsp;each&nbsp;bit&nbsp;or&nbsp;set&nbsp;of&nbsp;bits&nbsp;within&nbsp;the&nbsp;regist&nbsp;<br />
er&nbsp;<br />
controls&nbsp;some&nbsp;behavior&nbsp;of&nbsp;the&nbsp;larger&nbsp;device.&nbsp;<br />
relocatable&nbsp;<br />
A&nbsp;file&nbsp;containing&nbsp;object&nbsp;code&nbsp;that&nbsp;is&nbsp;almost&nbsp;ready&nbsp;for&nbsp;execution&nbsp;on&nbsp;the&nbsp;targ&nbsp;<br />
et.&nbsp;The&nbsp;<br />
final&nbsp;step&nbsp;is&nbsp;to&nbsp;use&nbsp;a&nbsp;locator&nbsp;to&nbsp;fix&nbsp;the&nbsp;remaining&nbsp;relocatable&nbsp;addresses&nbsp;wi&nbsp;<br />
thin&nbsp;the&nbsp;<br />
code.&nbsp;The&nbsp;result&nbsp;of&nbsp;that&nbsp;process&nbsp;is&nbsp;an&nbsp;executable.&nbsp;<br />
reset&nbsp;address&nbsp;<br />
The&nbsp;address&nbsp;from&nbsp;which&nbsp;the&nbsp;first&nbsp;instruction&nbsp;will&nbsp;be&nbsp;fetched&nbsp;after&nbsp;the&nbsp;proce&nbsp;<br />
ssor&nbsp;<br />
is&nbsp;powered&nbsp;on&nbsp;or&nbsp;reset.&nbsp;<br />
reset&nbsp;code&nbsp;<br />
A&nbsp;small&nbsp;piece&nbsp;of&nbsp;code&nbsp;that&nbsp;is&nbsp;placed&nbsp;at&nbsp;the&nbsp;reset&nbsp;address.&nbsp;The&nbsp;reset&nbsp;code&nbsp;is&nbsp;<br />
&nbsp;usually&nbsp;<br />
written&nbsp;in&nbsp;assembly&nbsp;language&nbsp;and&nbsp;may&nbsp;simply&nbsp;be&nbsp;the&nbsp;equivalent&nbsp;of&nbsp;&quot;jump&nbsp;to&nbsp;th&nbsp;<br />
e&nbsp;<br />
startup&nbsp;code.&quot;&nbsp;<br />
reset&nbsp;vector&nbsp;<br />
See&nbsp;reset&nbsp;address.&nbsp;<br />
S&nbsp;<br />
SRAM&nbsp;<br />
Static&nbsp;Random-Access&nbsp;Memory.&nbsp;A&nbsp;type&nbsp;of&nbsp;RAM&nbsp;that&nbsp;retains&nbsp;its&nbsp;contents&nbsp;as&nbsp;long&nbsp;<br />
&nbsp;as&nbsp;<br />
the&nbsp;system&nbsp;is&nbsp;powered&nbsp;on.&nbsp;Data&nbsp;stored&nbsp;in&nbsp;an&nbsp;SRAM&nbsp;is&nbsp;lost&nbsp;when&nbsp;the&nbsp;system&nbsp;is&nbsp;<br />
powered&nbsp;down&nbsp;or&nbsp;reset.&nbsp;<br />
scheduler&nbsp;<br />
The&nbsp;part&nbsp;of&nbsp;an&nbsp;operating&nbsp;system&nbsp;that&nbsp;decides&nbsp;which&nbsp;task&nbsp;to&nbsp;run&nbsp;next.&nbsp;This&nbsp;de&nbsp;<br />
cision&nbsp;<br />
is&nbsp;based&nbsp;on&nbsp;the&nbsp;readiness&nbsp;of&nbsp;each&nbsp;task,&nbsp;their&nbsp;relative&nbsp;priorities,&nbsp;and&nbsp;the&nbsp;s&nbsp;<br />
pecific&nbsp;<br />
scheduling&nbsp;algorithm&nbsp;implemented.&nbsp;<br />
semaphore&nbsp;<br />
A&nbsp;data&nbsp;structure&nbsp;that&nbsp;is&nbsp;used&nbsp;for&nbsp;intertask&nbsp;synchronization.&nbsp;Semaphores&nbsp;are&nbsp;<br />
usually&nbsp;provided&nbsp;by&nbsp;the&nbsp;operating&nbsp;system.&nbsp;<br />
simulator&nbsp;<br />
A&nbsp;debugging&nbsp;tool&nbsp;that&nbsp;runs&nbsp;on&nbsp;the&nbsp;host&nbsp;and&nbsp;pretends&nbsp;to&nbsp;be&nbsp;the&nbsp;target&nbsp;process&nbsp;<br />
or.&nbsp;A&nbsp;<br />
simulator&nbsp;can&nbsp;be&nbsp;used&nbsp;to&nbsp;test&nbsp;pieces&nbsp;of&nbsp;the&nbsp;software&nbsp;before&nbsp;the&nbsp;embedded&nbsp;<br />
hardware&nbsp;is&nbsp;available.&nbsp;Unfortunately,&nbsp;attempts&nbsp;to&nbsp;simulate&nbsp;interactions&nbsp;with&nbsp;<br />
&nbsp;<br />
complex&nbsp;peripherals&nbsp;are&nbsp;often&nbsp;more&nbsp;trouble&nbsp;than&nbsp;they&nbsp;are&nbsp;worth.&nbsp;<br />
software&nbsp;interrupt&nbsp;<br />
An&nbsp;interruption&nbsp;of&nbsp;a&nbsp;program&nbsp;that&nbsp;is&nbsp;initiated&nbsp;by&nbsp;a&nbsp;software&nbsp;instruction.&nbsp;So&nbsp;<br />
ftware&nbsp;<br />
interrupts&nbsp;are&nbsp;commonly&nbsp;used&nbsp;to&nbsp;implement&nbsp;breakpoints&nbsp;and&nbsp;operating&nbsp;system&nbsp;<br />
entry&nbsp;points.&nbsp;Unlike&nbsp;true&nbsp;interrupts,&nbsp;they&nbsp;occur&nbsp;synchronously&nbsp;with&nbsp;respect&nbsp;&nbsp;<br />
to&nbsp;<br />
program&nbsp;execution.&nbsp;In&nbsp;other&nbsp;words,&nbsp;software&nbsp;interrupts&nbsp;always&nbsp;occur&nbsp;at&nbsp;the&nbsp;<br />
beginning&nbsp;of&nbsp;an&nbsp;instruction&nbsp;execution&nbsp;cycle.&nbsp;Compare&nbsp;with&nbsp;trap.&nbsp;<br />
stack&nbsp;<br />
An&nbsp;area&nbsp;of&nbsp;memory&nbsp;that&nbsp;contains&nbsp;a&nbsp;last-in-first-out&nbsp;queue&nbsp;of&nbsp;storage&nbsp;for&nbsp;<br />
parameters,&nbsp;automatic&nbsp;variables,&nbsp;return&nbsp;addresses,&nbsp;and&nbsp;other&nbsp;information&nbsp;tha&nbsp;<br />
t&nbsp;<br />
must&nbsp;be&nbsp;maintained&nbsp;across&nbsp;function&nbsp;calls.&nbsp;In&nbsp;multitasking&nbsp;situations,&nbsp;each&nbsp;t&nbsp;<br />
ask&nbsp;<br />
generally&nbsp;has&nbsp;its&nbsp;own&nbsp;stack.&nbsp;<br />
stack&nbsp;frame&nbsp;<br />
An&nbsp;area&nbsp;of&nbsp;the&nbsp;stack&nbsp;associated&nbsp;with&nbsp;a&nbsp;particular&nbsp;function&nbsp;call.&nbsp;<br />
startup&nbsp;code&nbsp;<br />
A&nbsp;piece&nbsp;of&nbsp;assembly&nbsp;language&nbsp;code&nbsp;that&nbsp;prepares&nbsp;the&nbsp;way&nbsp;for&nbsp;software&nbsp;written&nbsp;<br />
&nbsp;in&nbsp;a&nbsp;<br />
high-level&nbsp;language.&nbsp;Most&nbsp;C/C++&nbsp;cross-compilers&nbsp;come&nbsp;with&nbsp;startup&nbsp;code&nbsp;that&nbsp;&nbsp;<br />
you&nbsp;<br />
can&nbsp;modify,&nbsp;compile,&nbsp;and&nbsp;link&nbsp;with&nbsp;your&nbsp;embedded&nbsp;programs.&nbsp;<br />
T&nbsp;<br />
target&nbsp;<br />
Another&nbsp;name&nbsp;for&nbsp;the&nbsp;embedded&nbsp;system.&nbsp;This&nbsp;term&nbsp;is&nbsp;usually&nbsp;used&nbsp;during&nbsp;softw&nbsp;<br />
are&nbsp;<br />
development,&nbsp;to&nbsp;distinguish&nbsp;the&nbsp;embedded&nbsp;system&nbsp;from&nbsp;the&nbsp;host&nbsp;with&nbsp;which&nbsp;it&nbsp;<br />
communicates.&nbsp;<br />
task&nbsp;<br />
The&nbsp;central&nbsp;abstraction&nbsp;of&nbsp;an&nbsp;operating&nbsp;system.&nbsp;Each&nbsp;task&nbsp;must&nbsp;maintain&nbsp;its&nbsp;&nbsp;<br />
own&nbsp;<br />
copy&nbsp;of&nbsp;the&nbsp;instruction&nbsp;pointer&nbsp;and&nbsp;general-purpose&nbsp;registers.&nbsp;Unlike&nbsp;proces&nbsp;<br />
ses,&nbsp;<br />
tasks&nbsp;share&nbsp;a&nbsp;common&nbsp;memory&nbsp;space&nbsp;and&nbsp;must&nbsp;be&nbsp;careful&nbsp;to&nbsp;avoid&nbsp;overwriting&nbsp;e&nbsp;<br />
ach&nbsp;<br />
other's&nbsp;code&nbsp;and&nbsp;data.&nbsp;<br />
thread&nbsp;<br />
Another&nbsp;name&nbsp;for&nbsp;a&nbsp;task.&nbsp;This&nbsp;name&nbsp;is&nbsp;more&nbsp;common&nbsp;in&nbsp;operating&nbsp;systems&nbsp;that&nbsp;<br />
support&nbsp;processes.&nbsp;A&nbsp;task&nbsp;is&nbsp;simply&nbsp;a&nbsp;thread&nbsp;in&nbsp;a&nbsp;single-process&nbsp;system.&nbsp;<br />
tracepoint&nbsp;<br />
Like&nbsp;a&nbsp;breakpoint&nbsp;except&nbsp;that&nbsp;a&nbsp;counter&nbsp;is&nbsp;incremented&nbsp;rather&nbsp;than&nbsp;stopping&nbsp;&nbsp;<br />
the&nbsp;<br />
program.&nbsp;Tracepoints&nbsp;are&nbsp;not&nbsp;supported&nbsp;by&nbsp;all&nbsp;debugging&nbsp;tools.&nbsp;<br />
trap&nbsp;<br />
An&nbsp;interruption&nbsp;of&nbsp;a&nbsp;program&nbsp;that&nbsp;is&nbsp;triggered&nbsp;by&nbsp;the&nbsp;processor's&nbsp;own&nbsp;intern&nbsp;<br />
al&nbsp;<br />
hardware.&nbsp;For&nbsp;example,&nbsp;the&nbsp;processor&nbsp;might&nbsp;trap&nbsp;if&nbsp;an&nbsp;illegal&nbsp;opcode&nbsp;is&nbsp;foun&nbsp;<br />
d&nbsp;<br />
within&nbsp;the&nbsp;program.&nbsp;Compare&nbsp;with&nbsp;software&nbsp;interrupt.&nbsp;<br />
V&nbsp;<br />
volatile&nbsp;<br />
A&nbsp;value&nbsp;that&nbsp;may&nbsp;change&nbsp;without&nbsp;the&nbsp;intervention&nbsp;of&nbsp;software&nbsp;is&nbsp;said&nbsp;to&nbsp;be&nbsp;v&nbsp;<br />
olatile.&nbsp;<br />
For&nbsp;example,&nbsp;values&nbsp;within&nbsp;the&nbsp;registers&nbsp;of&nbsp;some&nbsp;I/O&nbsp;devices&nbsp;may&nbsp;change&nbsp;in&nbsp;<br />
response&nbsp;to&nbsp;external&nbsp;events.&nbsp;C's&nbsp;volatile&nbsp;keyword&nbsp;should&nbsp;be&nbsp;used&nbsp;to&nbsp;warn&nbsp;you&nbsp;<br />
r&nbsp;<br />
compiler&nbsp;about&nbsp;any&nbsp;pointers&nbsp;that&nbsp;point&nbsp;to&nbsp;such&nbsp;registers.&nbsp;This&nbsp;will&nbsp;ensure&nbsp;t&nbsp;<br />
hat&nbsp;the&nbsp;<br />
actual&nbsp;value&nbsp;is&nbsp;reread&nbsp;each&nbsp;time&nbsp;the&nbsp;data&nbsp;is&nbsp;used.&nbsp;<br />
W&nbsp;<br />
watchdog&nbsp;timer&nbsp;<br />
A&nbsp;hardware&nbsp;timer&nbsp;that&nbsp;is&nbsp;periodically&nbsp;reset&nbsp;by&nbsp;software.&nbsp;If&nbsp;the&nbsp;software&nbsp;cra&nbsp;<br />
shes&nbsp;<br />
or&nbsp;hangs,&nbsp;the&nbsp;watchdog&nbsp;timer&nbsp;will&nbsp;expire,&nbsp;and&nbsp;the&nbsp;entire&nbsp;system&nbsp;will&nbsp;be&nbsp;rese&nbsp;<br />
t&nbsp;<br />
automatically.&nbsp;<br />
&nbsp;<br />
--&nbsp;<br />
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