📄 00000005.htm

📁 水木社区 embeded 版精华区下载
💻 HTM
字号:
<?xml version="1.0" encoding="gb2312"?><!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=gb2312"/><title>BDM手册5                               turbolinux </title></head><body><center><h1>BBS 水木清华站∶精华区</h1></center><a name="top"></a>发信人:&nbsp;doot&nbsp;(ltt),&nbsp;信区:&nbsp;Embedded&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<br />标&nbsp;&nbsp;题:&nbsp;BDM手册5&nbsp;<br />发信站:&nbsp;BBS&nbsp;水木清华站&nbsp;(Thu&nbsp;Oct&nbsp;26&nbsp;16:23:32&nbsp;2000)&nbsp;<br />&nbsp;<br />Embedded&nbsp;PowerPC&nbsp;BDM&nbsp;(Motorola&nbsp;MPC5xx,&nbsp;MPC8xx)&nbsp;<br />This&nbsp;BDM&nbsp;works&nbsp;quite&nbsp;differently&nbsp;from&nbsp;the&nbsp;CPU32&nbsp;type&nbsp;of&nbsp;BDM.&nbsp;The&nbsp;hardware&nbsp;in&nbsp;<br />terface&nbsp;<br />is&nbsp;similar&nbsp;with&nbsp;serial&nbsp;in,&nbsp;serial&nbsp;out,&nbsp;clock,&nbsp;reset,&nbsp;and&nbsp;status&nbsp;signals.&nbsp;The&nbsp;<br />&nbsp;difference&nbsp;is&nbsp;that&nbsp;<br />there&nbsp;is&nbsp;not&nbsp;a&nbsp;specific&nbsp;command&nbsp;set.&nbsp;Any&nbsp;serial&nbsp;stream&nbsp;entered&nbsp;into&nbsp;the&nbsp;chip&nbsp;<br />&nbsp;is&nbsp;either&nbsp;7&nbsp;or&nbsp;<br />32&nbsp;bits&nbsp;in&nbsp;length&nbsp;(not&nbsp;counting&nbsp;start,&nbsp;control,&nbsp;and&nbsp;length&nbsp;bits).&nbsp;Thirty-&nbsp;tw&nbsp;<br />o-&nbsp;bit&nbsp;bit&nbsp;streams&nbsp;<br />go&nbsp;into&nbsp;the&nbsp;instruction&nbsp;stuff&nbsp;register&nbsp;and&nbsp;come&nbsp;out&nbsp;of&nbsp;the&nbsp;debug&nbsp;data&nbsp;regist&nbsp;<br />er.&nbsp;What&nbsp;<br />actually&nbsp;happens&nbsp;is&nbsp;that&nbsp;the&nbsp;host&nbsp;debugger&nbsp;stuffs&nbsp;PowerPC&nbsp;opcodes&nbsp;into&nbsp;the&nbsp;p&nbsp;<br />rocessor&nbsp;and&nbsp;<br />they&nbsp;are&nbsp;executed.&nbsp;This&nbsp;is&nbsp;actually&nbsp;a&nbsp;very&nbsp;powerful&nbsp;design&nbsp;allowing&nbsp;for&nbsp;all&nbsp;&nbsp;<br />system&nbsp;resources&nbsp;<br />to&nbsp;be&nbsp;accessible&nbsp;since&nbsp;this&nbsp;method&nbsp;gives&nbsp;the&nbsp;debug&nbsp;port&nbsp;the&nbsp;same&nbsp;power&nbsp;as&nbsp;ex&nbsp;<br />ecuting&nbsp;<br />system&nbsp;code.&nbsp;Seven&nbsp;bit&nbsp;data&nbsp;streams&nbsp;are&nbsp;used&nbsp;to&nbsp;control&nbsp;on&nbsp;chip&nbsp;breakpoint&nbsp;f&nbsp;<br />unctions.&nbsp;<br />Debug&nbsp;control&nbsp;registers&nbsp;exist&nbsp;to&nbsp;enable&nbsp;single&nbsp;stepping&nbsp;and&nbsp;other&nbsp;special&nbsp;co&nbsp;<br />ntrols.&nbsp;<br />The&nbsp;processor&nbsp;is&nbsp;“aware”&nbsp;of&nbsp;this&nbsp;BDM&nbsp;in&nbsp;that&nbsp;it&nbsp;is&nbsp;a&nbsp;CPU&nbsp;exception.&nbsp;BDM&nbsp;ma&nbsp;<br />y&nbsp;be&nbsp;entered&nbsp;<br />upon&nbsp;one&nbsp;of&nbsp;any&nbsp;number&nbsp;of&nbsp;exception&nbsp;causing&nbsp;events&nbsp;(invalid&nbsp;opcode,&nbsp;address&nbsp;&nbsp;<br />bus&nbsp;<br />misalignment,&nbsp;non-&nbsp;maskable&nbsp;interrupt,&nbsp;etc.)&nbsp;To&nbsp;resume&nbsp;real-&nbsp;time&nbsp;execution,&nbsp;<br />&nbsp;the&nbsp;debugger&nbsp;<br />stuffs&nbsp;a&nbsp;“return&nbsp;from&nbsp;exception”&nbsp;instruction,&nbsp;“RFI”&nbsp;into&nbsp;the&nbsp;processor’&nbsp;<br />s&nbsp;instruction&nbsp;register.&nbsp;<br />OnCE&nbsp;(On-&nbsp;Chip&nbsp;Emulation)&nbsp;<br />The&nbsp;OnCE&nbsp;(On-&nbsp;Chip&nbsp;Emulation)&nbsp;interface&nbsp;is&nbsp;found&nbsp;on&nbsp;Motorola’s&nbsp;family&nbsp;of&nbsp;DS&nbsp;<br />P&nbsp;chips.&nbsp;It&nbsp;<br />allows&nbsp;for&nbsp;all&nbsp;the&nbsp;same&nbsp;type&nbsp;of&nbsp;debugging&nbsp;as&nbsp;the&nbsp;BDM&nbsp;interface.&nbsp;On&nbsp;most&nbsp;of&nbsp;t&nbsp;<br />he&nbsp;chips,&nbsp;the&nbsp;<br />OnCE&nbsp;interface&nbsp;is&nbsp;implemented&nbsp;via&nbsp;dedicated&nbsp;pins.&nbsp;On&nbsp;the&nbsp;more&nbsp;recent&nbsp;parts,&nbsp;&nbsp;<br />the&nbsp;OnCE&nbsp;<br />engine&nbsp;is&nbsp;accessed&nbsp;via&nbsp;the&nbsp;JTAG&nbsp;port&nbsp;pins.&nbsp;The&nbsp;OnCE&nbsp;port&nbsp;is&nbsp;more&nbsp;complex&nbsp;tha&nbsp;<br />n&nbsp;the&nbsp;BDM&nbsp;<br />port&nbsp;in&nbsp;that&nbsp;it&nbsp;is&nbsp;a&nbsp;state&nbsp;machine&nbsp;controlled&nbsp;by&nbsp;the&nbsp;external&nbsp;debugger.&nbsp;The&nbsp;&nbsp;<br />capabilities&nbsp;of&nbsp;<br />OnCE&nbsp;include:&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Interrupt/&nbsp;break&nbsp;into&nbsp;debug&nbsp;mode&nbsp;on&nbsp;program&nbsp;memory&nbsp;address&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Interrupt/&nbsp;break&nbsp;into&nbsp;debug&nbsp;node&nbsp;on&nbsp;data&nbsp;memory&nbsp;address&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Interrupt/&nbsp;break&nbsp;into&nbsp;debug&nbsp;mode&nbsp;on&nbsp;an&nbsp;on-&nbsp;chip&nbsp;peripheral&nbsp;access&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Enter&nbsp;debug&nbsp;mode&nbsp;using&nbsp;a&nbsp;DSP&nbsp;microprocessor&nbsp;instruction&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Read/&nbsp;write&nbsp;any&nbsp;DSP&nbsp;core&nbsp;register&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Read/&nbsp;write&nbsp;peripheral&nbsp;memory&nbsp;mapped&nbsp;registers&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Read/&nbsp;write&nbsp;program&nbsp;or&nbsp;data&nbsp;memory&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Step&nbsp;one&nbsp;or&nbsp;more&nbsp;instructions&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Trace&nbsp;one&nbsp;or&nbsp;more&nbsp;instructions&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Save&nbsp;or&nbsp;restore&nbsp;current&nbsp;chip&nbsp;pipeline&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Read&nbsp;real-&nbsp;time&nbsp;instruction&nbsp;trace&nbsp;buffer&nbsp;<br />&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Exit&nbsp;debug&nbsp;mode&nbsp;<br />JTAG&nbsp;debugging&nbsp;(PPC6xx,&nbsp;IBM&nbsp;4xx,&nbsp;TI&nbsp;C90,&nbsp;Analog&nbsp;Devices&nbsp;SHARC)&nbsp;<br />JTAG&nbsp;(Joint&nbsp;Test&nbsp;Action&nbsp;Group.&nbsp;pronounced&nbsp;“jay-&nbsp;tag”)&nbsp;is&nbsp;an&nbsp;IEEE&nbsp;specifica&nbsp;<br />tion&nbsp;(IEEE&nbsp;<br />1149.1).&nbsp;It&nbsp;is&nbsp;actually&nbsp;a&nbsp;method&nbsp;for&nbsp;doing&nbsp;full&nbsp;chip&nbsp;testing&nbsp;and&nbsp;was&nbsp;origina&nbsp;<br />lly&nbsp;implemented&nbsp;<br />to&nbsp;allow&nbsp;testing&nbsp;of&nbsp;all&nbsp;the&nbsp;pin&nbsp;connections&nbsp;of&nbsp;a&nbsp;chip&nbsp;and&nbsp;its&nbsp;interconnectio&nbsp;<br />ns&nbsp;to&nbsp;other&nbsp;chips&nbsp;<br />on&nbsp;the&nbsp;circuit&nbsp;board.&nbsp;It&nbsp;is&nbsp;a&nbsp;serial&nbsp;protocol&nbsp;and&nbsp;chips&nbsp;on&nbsp;the&nbsp;board&nbsp;may&nbsp;be&nbsp;&nbsp;<br />daisy-&nbsp;chained&nbsp;<br />together.&nbsp;In&nbsp;simple&nbsp;terms,&nbsp;the&nbsp;JTAG&nbsp;serial&nbsp;chain&nbsp;through&nbsp;the&nbsp;chip&nbsp;may&nbsp;be&nbsp;wir&nbsp;<br />ed&nbsp;through&nbsp;<br />any&nbsp;on&nbsp;chip&nbsp;devices&nbsp;but&nbsp;typically&nbsp;minimally&nbsp;connects&nbsp;to&nbsp;all&nbsp;the&nbsp;I/&nbsp;O&nbsp;pins&nbsp;an&nbsp;<br />d&nbsp;buffers.&nbsp;The&nbsp;<br />chain&nbsp;may&nbsp;be&nbsp;several&nbsp;score&nbsp;long&nbsp;or&nbsp;thousands&nbsp;of&nbsp;elements.&nbsp;There&nbsp;is&nbsp;no&nbsp;specif&nbsp;<br />ication&nbsp;stating&nbsp;<br />any&nbsp;inclusion&nbsp;of&nbsp;resources&nbsp;for&nbsp;software&nbsp;debug&nbsp;nor&nbsp;is&nbsp;there&nbsp;a&nbsp;prohibition.&nbsp;<br />Different&nbsp;processors&nbsp;implement&nbsp;OCD&nbsp;via&nbsp;JTAG&nbsp;in&nbsp;different&nbsp;ways.&nbsp;The&nbsp;600&nbsp;serie&nbsp;<br />s&nbsp;of&nbsp;PowerPC&nbsp;<br />microprocessors&nbsp;purely&nbsp;use&nbsp;the&nbsp;hardware&nbsp;test&nbsp;chain&nbsp;which&nbsp;winds&nbsp;its&nbsp;way&nbsp;throu&nbsp;<br />gh&nbsp;many&nbsp;of&nbsp;<br />the&nbsp;on-&nbsp;chip&nbsp;resources.&nbsp;Somewhere&nbsp;in&nbsp;the&nbsp;multi-&nbsp;thousand&nbsp;stage&nbsp;serial&nbsp;chain&nbsp;&nbsp;<br />is&nbsp;the&nbsp;instruction&nbsp;<br />register,&nbsp;for&nbsp;example.&nbsp;Debugging&nbsp;with&nbsp;this&nbsp;system&nbsp;is&nbsp;tedious&nbsp;since&nbsp;each&nbsp;core&nbsp;<br />&nbsp;OCD&nbsp;action&nbsp;<br />(modify&nbsp;memory&nbsp;location&nbsp;for&nbsp;instance)&nbsp;may&nbsp;take&nbsp;many&nbsp;trips&nbsp;through&nbsp;the&nbsp;entire&nbsp;<br />&nbsp;JTAG&nbsp;<br />chain.&nbsp;Although&nbsp;the&nbsp;debugger&nbsp;may&nbsp;only&nbsp;be&nbsp;interested&nbsp;in&nbsp;a&nbsp;32&nbsp;bit&nbsp;piece&nbsp;of&nbsp;the&nbsp;<br />&nbsp;chain,&nbsp;all&nbsp;<br />elements&nbsp;must&nbsp;be&nbsp;traversed,&nbsp;and&nbsp;multiple&nbsp;times.&nbsp;Downloading&nbsp;user&nbsp;code&nbsp;may&nbsp;be&nbsp;<br />&nbsp;as&nbsp;slow&nbsp;as&nbsp;<br />less&nbsp;than&nbsp;one&nbsp;hundred&nbsp;bytes&nbsp;per&nbsp;second&nbsp;(vs.&nbsp;over&nbsp;20K&nbsp;per&nbsp;second&nbsp;with&nbsp;other&nbsp;m&nbsp;<br />ethods).&nbsp;<br />Another&nbsp;drawback&nbsp;to&nbsp;implementations&nbsp;that&nbsp;use&nbsp;a&nbsp;shared&nbsp;hardware&nbsp;test/&nbsp;softwar&nbsp;<br />e&nbsp;debug&nbsp;<br />chain&nbsp;(TI&nbsp;DSP&nbsp;chips,&nbsp;600&nbsp;family&nbsp;PowerPC,&nbsp;etc.)&nbsp;is&nbsp;the&nbsp;way&nbsp;the&nbsp;chain&nbsp;is&nbsp;route&nbsp;<br />d&nbsp;during&nbsp;chip&nbsp;<br />design.&nbsp;Since&nbsp;this&nbsp;is&nbsp;typically&nbsp;the&nbsp;least&nbsp;critical&nbsp;path&nbsp;and&nbsp;the&nbsp;least&nbsp;critic&nbsp;<br />al&nbsp;part&nbsp;of&nbsp;the&nbsp;chip&nbsp;<br />design/&nbsp;layout&nbsp;(as&nbsp;well&nbsp;it&nbsp;should&nbsp;be),&nbsp;the&nbsp;designers&nbsp;let&nbsp;the&nbsp;silicon&nbsp;auto-&nbsp;r&nbsp;<br />outer&nbsp;layout&nbsp;the&nbsp;<br />chain’s&nbsp;pathway&nbsp;after&nbsp;the&nbsp;rest&nbsp;of&nbsp;the&nbsp;chip&nbsp;has&nbsp;been&nbsp;laid&nbsp;out.&nbsp;This&nbsp;means&nbsp;th&nbsp;<br />at&nbsp;each&nbsp;revision&nbsp;<br />of&nbsp;the&nbsp;silicon&nbsp;may&nbsp;have&nbsp;a&nbsp;different&nbsp;JTAG&nbsp;chain,&nbsp;hence&nbsp;the&nbsp;host&nbsp;debugger&nbsp;soft&nbsp;<br />ware&nbsp;must&nbsp;be&nbsp;<br />aware&nbsp;of&nbsp;every&nbsp;revision&nbsp;of&nbsp;silicon.&nbsp;This&nbsp;is&nbsp;a&nbsp;nightmare.&nbsp;TI&nbsp;solves&nbsp;this&nbsp;prob&nbsp;<br />lem&nbsp;by&nbsp;often&nbsp;<br />updating&nbsp;their&nbsp;OEM&nbsp;emulator&nbsp;software&nbsp;tool&nbsp;kit.&nbsp;This&nbsp;does&nbsp;not&nbsp;help&nbsp;the&nbsp;end-&nbsp;u&nbsp;<br />ser&nbsp;unless&nbsp;<br />he/&nbsp;she&nbsp;has&nbsp;a&nbsp;very&nbsp;reliable&nbsp;debugger&nbsp;vendor.&nbsp;<br />An&nbsp;alternative&nbsp;method&nbsp;to&nbsp;the&nbsp;JTAG&nbsp;OCD&nbsp;is&nbsp;to&nbsp;use&nbsp;a&nbsp;different&nbsp;chain&nbsp;via&nbsp;the&nbsp;JT&nbsp;<br />AG&nbsp;port.&nbsp;<br />This&nbsp;is&nbsp;allowed&nbsp;for&nbsp;in&nbsp;the&nbsp;IEEE&nbsp;specification.&nbsp;Using&nbsp;this&nbsp;method,&nbsp;one&nbsp;chain&nbsp;&nbsp;<br />is&nbsp;available&nbsp;for&nbsp;<br />the&nbsp;hardware&nbsp;test&nbsp;and&nbsp;debug&nbsp;of&nbsp;the&nbsp;chip,&nbsp;another&nbsp;for&nbsp;software&nbsp;debug.&nbsp;This&nbsp;me&nbsp;<br />thod&nbsp;is&nbsp;used&nbsp;<br />in&nbsp;the&nbsp;IBM&nbsp;400&nbsp;series&nbsp;of&nbsp;PowerPC&nbsp;as&nbsp;well&nbsp;as&nbsp;in&nbsp;the&nbsp;SHARC&nbsp;DSP&nbsp;from&nbsp;Analog&nbsp;Dev&nbsp;<br />ices.&nbsp;<br />This&nbsp;secondary&nbsp;chain&nbsp;allows&nbsp;access&nbsp;to&nbsp;debug&nbsp;specific&nbsp;registers,&nbsp;usually&nbsp;only&nbsp;<br />&nbsp;two&nbsp;or&nbsp;three&nbsp;<br />are&nbsp;needed.&nbsp;In&nbsp;the&nbsp;IBM&nbsp;chips,&nbsp;the&nbsp;debug&nbsp;port&nbsp;has&nbsp;access&nbsp;to&nbsp;an&nbsp;instruction&nbsp;st&nbsp;<br />uff&nbsp;buffer,&nbsp;a&nbsp;<br />debug&nbsp;control&nbsp;register&nbsp;and&nbsp;a&nbsp;debug&nbsp;status&nbsp;register.&nbsp;The&nbsp;instruction&nbsp;stuff&nbsp;bu&nbsp;<br />ffer&nbsp;allows&nbsp;the&nbsp;<br />debugger&nbsp;to&nbsp;stuff&nbsp;any&nbsp;opcode&nbsp;into&nbsp;the&nbsp;core&nbsp;processors’&nbsp;instruction&nbsp;register&nbsp;<br />,&nbsp;in&nbsp;effect&nbsp;causing&nbsp;<br />a&nbsp;single&nbsp;step&nbsp;to&nbsp;occur.&nbsp;By&nbsp;executing&nbsp;the&nbsp;proper&nbsp;instructions,&nbsp;any&nbsp;action&nbsp;nee&nbsp;<br />ded&nbsp;may&nbsp;be&nbsp;<br />performed.&nbsp;The&nbsp;debug&nbsp;control&nbsp;and&nbsp;status&nbsp;registers&nbsp;allow&nbsp;for&nbsp;the&nbsp;typical&nbsp;debu&nbsp;<br />g&nbsp;commands&nbsp;<br />such&nbsp;as&nbsp;single&nbsp;step&nbsp;and&nbsp;run.&nbsp;Since&nbsp;a&nbsp;chain&nbsp;separate&nbsp;from&nbsp;the&nbsp;hardware&nbsp;test&nbsp;c&nbsp;<br />hain&nbsp;is&nbsp;used,&nbsp;<br />the&nbsp;length&nbsp;of&nbsp;the&nbsp;chain&nbsp;is&nbsp;typically&nbsp;under&nbsp;50&nbsp;bits&nbsp;long.&nbsp;There&nbsp;is&nbsp;some&nbsp;small&nbsp;<br />&nbsp;overhead&nbsp;with&nbsp;<br />each&nbsp;JTAG&nbsp;action&nbsp;to&nbsp;ensure&nbsp;that&nbsp;the&nbsp;proper&nbsp;chain&nbsp;is&nbsp;being&nbsp;accessed.&nbsp;<br />Note&nbsp;that&nbsp;TI&nbsp;uses&nbsp;different&nbsp;flavors&nbsp;of&nbsp;the&nbsp;JTAG&nbsp;port&nbsp;on&nbsp;the&nbsp;DSP&nbsp;chips.&nbsp;The&nbsp;C&nbsp;<br />30&nbsp;family&nbsp;<br />actually&nbsp;has&nbsp;what&nbsp;is&nbsp;referred&nbsp;to&nbsp;as&nbsp;an&nbsp;MPSD&nbsp;port,&nbsp;similar&nbsp;but&nbsp;not&nbsp;exactly&nbsp;JT&nbsp;<br />AG.&nbsp;<br />An&nbsp;advantage&nbsp;to&nbsp;using&nbsp;the&nbsp;JTAG&nbsp;port&nbsp;for&nbsp;software&nbsp;debug&nbsp;is&nbsp;that&nbsp;it&nbsp;does&nbsp;not&nbsp;n&nbsp;<br />eed&nbsp;any&nbsp;<br />additional&nbsp;pins&nbsp;on&nbsp;the&nbsp;processor&nbsp;for&nbsp;separate&nbsp;hardware&nbsp;and&nbsp;software&nbsp;debug.&nbsp;A&nbsp;<br />&nbsp;disadvantage&nbsp;<br />is&nbsp;the&nbsp;added&nbsp;overhead&nbsp;needed&nbsp;for&nbsp;each&nbsp;basic&nbsp;action.&nbsp;<br />&nbsp;<br />--&nbsp;<br />&nbsp;<br />※&nbsp;来源:·BBS&nbsp;水木清华站&nbsp;smth.org·[FROM:&nbsp;202.117.114.7]&nbsp;<br /><a href="00000004.htm">上一篇</a><a href="javascript:history.go(-1)">返回上一页</a><a href="index.htm">回到目录</a><a href="#top">回到页首</a><a href="00000006.htm">下一篇</a></h1></center><center><h1>BBS 水木清华站∶精华区</h1></center></body></html>
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -