c54.rpt

这是自制c5402开发板所有的资料

* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  d:\cpld1\c54.rpt
c54

** EQUATIONS **

AD_EOC   : INPUT;
ALL_RESET : INPUT;
CODEC_MCLK : INPUT;
DSP_A0   : INPUT;
DSP_A1   : INPUT;
DSP_A2   : INPUT;
DSP_A3   : INPUT;
DSP_A14  : INPUT;
DSP_A15  : INPUT;
DSP_A16  : INPUT;
DSP_A17  : INPUT;
DSP_A18  : INPUT;
DSP_CLKOUT : INPUT;
DSP_DS   : INPUT;
DSP_D0   : INPUT;
DSP_D1   : INPUT;
DSP_D2   : INPUT;
DSP_D3   : INPUT;
DSP_D4   : INPUT;
DSP_D5   : INPUT;
DSP_D6   : INPUT;
DSP_D7   : INPUT;
DSP_IAQ  : INPUT;
DSP_ICAK : INPUT;
DSP_IOSTRB : INPUT;
DSP_IS   : INPUT;
DSP_MSC  : INPUT;
DSP_MSTRB : INPUT;
DSP_PS   : INPUT;
DSP_R/W  : INPUT;
DSP_TOUT0 : INPUT;
DSP_XF   : INPUT;
FLASH_RY/BY : INPUT;
PCI_HINT0 : INPUT;
PCI_HRST0 : INPUT;

-- Node name is 'AD_CONVST' 
-- Equation name is 'AD_CONVST', location is LC121, type is output.
 AD_CONVST = LCELL( _EQ001 $  VCC);
  _EQ001 = !DSP_A0 &  DSP_A1 &  DSP_A2 & !DSP_A3 & !DSP_IOSTRB & !DSP_IS;

-- Node name is 'AD_CS' 
-- Equation name is 'AD_CS', location is LC123, type is output.
 AD_CS   = LCELL( _EQ002 $  VCC);
  _EQ002 =  DSP_A2 & !DSP_A3 & !DSP_IOSTRB & !DSP_IS;

-- Node name is 'AD_PD' 
-- Equation name is 'AD_PD', location is LC128, type is output.
 AD_PD   = LCELL( _EQ003 $  VCC);
  _EQ003 =  DSP_A0 & !DSP_A1 &  DSP_A2 & !DSP_A3 & !DSP_IOSTRB & !DSP_IS;

-- Node name is 'AD_RD' 
-- Equation name is 'AD_RD', location is LC125, type is output.
 AD_RD   = LCELL( _EQ004 $  VCC);
  _EQ004 =  DSP_A0 &  DSP_A1 &  DSP_A2 & !DSP_A3 & !DSP_IOSTRB & !DSP_IS;

-- Node name is 'CODEC_FC' 
-- Equation name is 'CODEC_FC', location is LC009, type is output.
 CODEC_FC = LCELL( GND $  GND);

-- Node name is 'CODEC_RESET' 
-- Equation name is 'CODEC_RESET', location is LC011, type is output.
 CODEC_RESET = LCELL( _EQ005 $  VCC);
  _EQ005 =  DSP_A0 &  DSP_A1 &  DSP_A2 &  DSP_A3 & !DSP_IOSTRB & !DSP_IS;

-- Node name is 'DA_CS' 
-- Equation name is 'DA_CS', location is LC014, type is output.
 DA_CS   = LCELL( _EQ006 $  VCC);
  _EQ006 = !DSP_A1 & !DSP_A2 &  DSP_A3 & !DSP_IOSTRB & !DSP_IS;

-- Node name is 'DA_WR' 
-- Equation name is 'DA_WR', location is LC013, type is output.
 DA_WR   = LCELL( _EQ007 $  VCC);
  _EQ007 =  DSP_A0 & !DSP_A1 & !DSP_A2 &  DSP_A3 & !DSP_IOSTRB & !DSP_IS;

-- Node name is 'DSP_BIO' 
-- Equation name is 'DSP_BIO', location is LC054, type is output.
 DSP_BIO = LCELL( GND $  VCC);

-- Node name is 'DSP_INT0' 
-- Equation name is 'DSP_INT0', location is LC022, type is output.
 DSP_INT0 = LCELL( GND $  VCC);

-- Node name is 'DSP_INT1' 
-- Equation name is 'DSP_INT1', location is LC021, type is output.
 DSP_INT1 = LCELL( GND $  VCC);

-- Node name is 'DSP_INT2' 
-- Equation name is 'DSP_INT2', location is LC019, type is output.
 DSP_INT2 = LCELL( PCI_HINT0 $  GND);

-- Node name is 'DSP_INT3' 
-- Equation name is 'DSP_INT3', location is LC017, type is output.
 DSP_INT3 = LCELL( AD_EOC $  GND);

-- Node name is 'DSP_MP/MC' 
-- Equation name is 'DSP_MP/MC', location is LC056, type is output.
 DSP_MP/MC = LCELL( GND $  VCC);

-- Node name is 'DSP_NMI' 
-- Equation name is 'DSP_NMI', location is LC024, type is output.
 DSP_NMI = LCELL( GND $  VCC);

-- Node name is 'DSP_READY' 
-- Equation name is 'DSP_READY', location is LC075, type is output.
 DSP_READY = LCELL( GND $  VCC);

-- Node name is 'DSP_RS' 
-- Equation name is 'DSP_RS', location is LC025, type is output.
 DSP_RS  = LCELL(!ALL_RESET $  GND);

-- Node name is 'FLASH_A14' 
-- Equation name is 'FLASH_A14', location is LC099, type is output.
 FLASH_A14 = LCELL( DSP_A14 $  GND);

-- Node name is 'FLASH_A15' 
-- Equation name is 'FLASH_A15', location is LC101, type is output.
 FLASH_A15 = LCELL( DSP_A15 $  GND);

-- Node name is 'FLASH_A16' 
-- Equation name is 'FLASH_A16', location is LC110, type is output.
 FLASH_A16 = LCELL( DSP_A16 $  GND);

-- Node name is 'FLASH_A17' 
-- Equation name is 'FLASH_A17', location is LC089, type is output.
 FLASH_A17 = LCELL( DSP_A17 $  GND);

-- Node name is 'FLASH_A18' 
-- Equation name is 'FLASH_A18', location is LC091, type is output.
 FLASH_A18 = LCELL( DSP_A18 $  GND);

-- Node name is 'FLASH_BYTE' 
-- Equation name is 'FLASH_BYTE', location is LC109, type is output.
 FLASH_BYTE = LCELL( GND $  VCC);

-- Node name is 'FLASH_CE' 
-- Equation name is 'FLASH_CE', location is LC117, type is output.
 FLASH_CE = LCELL( _EQ008 $  VCC);
  _EQ008 =  DSP_A15 & !DSP_A16 & !DSP_DS & !DSP_MSTRB &  DSP_PS
         #  DSP_A17 &  DSP_DS & !DSP_MSTRB & !DSP_PS
         #  DSP_A18 &  DSP_DS & !DSP_MSTRB & !DSP_PS;

-- Node name is 'FLASH_OE' 
-- Equation name is 'FLASH_OE', location is LC118, type is output.
 FLASH_OE = LCELL(!DSP_R/W $  GND);

-- Node name is 'FLASH_RESET' 
-- Equation name is 'FLASH_RESET', location is LC094, type is output.
 FLASH_RESET = LCELL( GND $  VCC);

-- Node name is 'FLASH_WE' 
-- Equation name is 'FLASH_WE', location is LC097, type is output.
 FLASH_WE = LCELL( DSP_R/W $  GND);

-- Node name is 'IO1' 
-- Equation name is 'IO1', location is LC001, type is output.
 IO1     = LCELL( GND $  GND);

-- Node name is 'IO2' 
-- Equation name is 'IO2', location is LC030, type is output.
 IO2     = LCELL( GND $  GND);

-- Node name is 'IO3' 
-- Equation name is 'IO3', location is LC029, type is output.
 IO3     = LCELL(!DSP_XF $  GND);

-- Node name is 'IO4' 
-- Equation name is 'IO4', location is LC027, type is output.
 IO4     = LCELL( GND $  GND);

-- Node name is 'LED1' 
-- Equation name is 'LED1', location is LC006, type is output.
 LED1    = LCELL(!ALL_RESET $  GND);

-- Node name is 'LED2' 
-- Equation name is 'LED2', location is LC005, type is output.
 LED2    = LCELL(!DSP_XF $  GND);

-- Node name is 'LED3' 
-- Equation name is 'LED3', location is LC003, type is output.
 LED3    = LCELL( GND $  VCC);

-- Node name is 'SRAM_A14' 
-- Equation name is 'SRAM_A14', location is LC102, type is output.
 SRAM_A14 = LCELL( DSP_A14 $  GND);

-- Node name is 'SRAM_A15' 
-- Equation name is 'SRAM_A15', location is LC104, type is output.
 SRAM_A15 = LCELL( DSP_A15 $  GND);

-- Node name is 'SRAM_A16' 
-- Equation name is 'SRAM_A16', location is LC105, type is output.
 SRAM_A16 = LCELL( DSP_A16 $  GND);

-- Node name is 'SRAM_CE' 
-- Equation name is 'SRAM_CE', location is LC081, type is output.
 SRAM_CE = LCELL( _EQ009 $  VCC);
  _EQ009 = !DSP_A17 & !DSP_A18 &  DSP_DS & !DSP_MSTRB & !DSP_PS;

-- Node name is 'SRAM_OE' 
-- Equation name is 'SRAM_OE', location is LC083, type is output.
 SRAM_OE = LCELL(!DSP_R/W $  GND);

-- Node name is 'SRAM_WE' 
-- Equation name is 'SRAM_WE', location is LC107, type is output.
 SRAM_WE = LCELL( DSP_R/W $  GND);

-- Node name is 'XBUS_ENA' 
-- Equation name is 'XBUS_ENA', location is LC120, type is output.
 XBUS_ENA = LCELL( DSP_IS $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                           d:\cpld1\c54.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = on
   Rules                                  = EPLD Rules


Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   Design Doctor                          00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,762K