📄 c54.rpt
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** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
86 (126) (H) INPUT 0 0 0 0 0 1 0 AD_EOC
94 (16) (A) INPUT 0 0 0 0 0 2 0 ALL_RESET
100 (8) (A) INPUT 0 0 0 0 0 0 0 CODEC_MCLK
77 (113) (H) INPUT 0 0 0 0 0 5 0 DSP_A0
56 (85) (F) INPUT 0 0 0 0 0 6 0 DSP_A1
57 (86) (F) INPUT 0 0 0 0 0 7 0 DSP_A2
58 (88) (F) INPUT 0 0 0 0 0 7 0 DSP_A3
51 (78) (E) INPUT 0 0 0 0 0 2 0 DSP_A14
50 (77) (E) INPUT 0 0 0 0 0 3 0 DSP_A15
29 (64) (D) INPUT 0 0 0 0 0 3 0 DSP_A16
30 (62) (D) INPUT 0 0 0 0 0 3 0 DSP_A17
31 (61) (D) INPUT 0 0 0 0 0 3 0 DSP_A18
19 (45) (C) INPUT 0 0 0 0 0 0 0 DSP_CLKOUT
47 (72) (E) INPUT 0 0 0 0 0 2 0 DSP_DS
21 (43) (C) INPUT 0 0 0 0 0 0 0 DSP_D0
23 (40) (C) INPUT 0 0 0 0 0 0 0 DSP_D1
24 (38) (C) INPUT 0 0 0 0 0 0 0 DSP_D2
25 (37) (C) INPUT 0 0 0 0 0 0 0 DSP_D3
26 (35) (C) INPUT 0 0 0 0 0 0 0 DSP_D4
27 (33) (C) INPUT 0 0 0 0 0 0 0 DSP_D5
33 (57) (D) INPUT 0 0 0 0 0 0 0 DSP_D6
32 (59) (D) INPUT 0 0 0 0 0 0 0 DSP_D7
37 (53) (D) INPUT 0 0 0 0 0 0 0 DSP_IAQ
22 (41) (C) INPUT 0 0 0 0 0 0 0 DSP_ICAK
42 (65) (E) INPUT 0 0 0 0 0 7 0 DSP_IOSTRB
46 (70) (E) INPUT 0 0 0 0 0 8 0 DSP_IS
39 (49) (D) INPUT 0 0 0 0 0 0 0 DSP_MSC
43 (67) (E) INPUT 0 0 0 0 0 2 0 DSP_MSTRB
48 (73) (E) INPUT 0 0 0 0 0 2 0 DSP_PS
44 (69) (E) INPUT 0 0 0 0 0 4 0 DSP_R/W
18 (46) (C) INPUT 0 0 0 0 0 0 0 DSP_TOUT0
38 (51) (D) INPUT 0 0 0 0 0 2 0 DSP_XF
62 (93) (F) INPUT 0 0 0 0 0 0 0 FLASH_RY/BY
52 (80) (E) INPUT 0 0 0 0 0 1 0 PCI_HINT0
78 (115) (H) INPUT 0 0 0 0 0 0 0 PCI_HRST0
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\cpld1\c54.rpt
c54
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
82 121 H OUTPUT t 0 0 0 6 0 0 0 AD_CONVST
83 123 H OUTPUT t 0 0 0 4 0 0 0 AD_CS
87 128 H OUTPUT t 0 0 0 6 0 0 0 AD_PD
85 125 H OUTPUT t 0 0 0 6 0 0 0 AD_RD
99 9 A OUTPUT t 0 0 0 0 0 0 0 CODEC_FC
98 11 A OUTPUT t 0 0 0 6 0 0 0 CODEC_RESET
95 14 A OUTPUT t 0 0 0 5 0 0 0 DA_CS
96 13 A OUTPUT t 0 0 0 6 0 0 0 DA_WR
35 54 D OUTPUT t 0 0 0 0 0 0 0 DSP_BIO
12 22 B OUTPUT t 0 0 0 0 0 0 0 DSP_INT0
14 21 B OUTPUT t 0 0 0 0 0 0 0 DSP_INT1
15 19 B OUTPUT t 0 0 0 1 0 0 0 DSP_INT2
16 17 B OUTPUT t 0 0 0 1 0 0 0 DSP_INT3
34 56 D OUTPUT t 0 0 0 0 0 0 0 DSP_MP/MC
11 24 B OUTPUT t 0 0 0 0 0 0 0 DSP_NMI
49 75 E OUTPUT t 0 0 0 0 0 0 0 DSP_READY
10 25 B OUTPUT t 0 0 0 1 0 0 0 DSP_RS
66 99 G OUTPUT t 0 0 0 1 0 0 0 FLASH_A14
67 101 G OUTPUT t 0 0 0 1 0 0 0 FLASH_A15
74 110 G OUTPUT t 0 0 0 1 0 0 0 FLASH_A16
59 89 F OUTPUT t 0 0 0 1 0 0 0 FLASH_A17
60 91 F OUTPUT t 0 0 0 1 0 0 0 FLASH_A18
73 109 G OUTPUT t 0 0 0 0 0 0 0 FLASH_BYTE
79 117 H OUTPUT t 0 0 0 7 0 0 0 FLASH_CE
80 118 H OUTPUT t 0 0 0 1 0 0 0 FLASH_OE
63 94 F OUTPUT t 0 0 0 0 0 0 0 FLASH_RESET
65 97 G OUTPUT t 0 0 0 1 0 0 0 FLASH_WE
4 1 A OUTPUT t 0 0 0 0 0 0 0 IO1
7 30 B OUTPUT t 0 0 0 0 0 0 0 IO2
8 29 B OUTPUT t 0 0 0 1 0 0 0 IO3
9 27 B OUTPUT t 0 0 0 0 0 0 0 IO4
1 6 A OUTPUT t 0 0 0 1 0 0 0 LED1
2 5 A OUTPUT t 0 0 0 1 0 0 0 LED2
3 3 A OUTPUT t 0 0 0 0 0 0 0 LED3
69 102 G OUTPUT t 0 0 0 1 0 0 0 SRAM_A14
70 104 G OUTPUT t 0 0 0 1 0 0 0 SRAM_A15
71 105 G OUTPUT t 0 0 0 1 0 0 0 SRAM_A16
54 81 F OUTPUT t 0 0 0 5 0 0 0 SRAM_CE
55 83 F OUTPUT t 0 0 0 1 0 0 0 SRAM_OE
72 107 G OUTPUT t 0 0 0 1 0 0 0 SRAM_WE
81 120 H OUTPUT t 0 0 0 1 0 0 0 XBUS_ENA
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\cpld1\c54.rpt
c54
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------- LC9 CODEC_FC
| +------------- LC11 CODEC_RESET
| | +----------- LC14 DA_CS
| | | +--------- LC13 DA_WR
| | | | +------- LC1 IO1
| | | | | +----- LC6 LED1
| | | | | | +--- LC5 LED2
| | | | | | | +- LC3 LED3
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'A'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
94 -> - - - - - * - - | * * - - - - - - | <-- ALL_RESET
77 -> - * - * - - - - | * - - - - - - * | <-- DSP_A0
56 -> - * * * - - - - | * - - - - - - * | <-- DSP_A1
57 -> - * * * - - - - | * - - - - - - * | <-- DSP_A2
58 -> - * * * - - - - | * - - - - - - * | <-- DSP_A3
42 -> - * * * - - - - | * - - - - - - * | <-- DSP_IOSTRB
46 -> - * * * - - - - | * - - - - - - * | <-- DSP_IS
38 -> - - - - - - * - | * * - - - - - - | <-- DSP_XF
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld1\c54.rpt
c54
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------- LC22 DSP_INT0
| +--------------- LC21 DSP_INT1
| | +------------- LC19 DSP_INT2
| | | +----------- LC17 DSP_INT3
| | | | +--------- LC24 DSP_NMI
| | | | | +------- LC25 DSP_RS
| | | | | | +----- LC30 IO2
| | | | | | | +--- LC29 IO3
| | | | | | | | +- LC27 IO4
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
Pin
86 -> - - - * - - - - - | - * - - - - - - | <-- AD_EOC
94 -> - - - - - * - - - | * * - - - - - - | <-- ALL_RESET
38 -> - - - - - - - * - | * * - - - - - - | <-- DSP_XF
52 -> - - * - - - - - - | - * - - - - - - | <-- PCI_HINT0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld1\c54.rpt
c54
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+--- LC54 DSP_BIO
| +- LC56 DSP_MP/MC
| |
| | Other LABs fed by signals
| | that feed LAB 'D'
LC | | | A B C D E F G H | Logic cells that feed LAB 'D':
Pin
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld1\c54.rpt
c54
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+- LC75 DSP_READY
|
| Other LABs fed by signals
| that feed LAB 'E'
LC | | A B C D E F G H | Logic cells that feed LAB 'E':
Pin
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld1\c54.rpt
c54
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+--------- LC89 FLASH_A17
| +------- LC91 FLASH_A18
| | +----- LC94 FLASH_RESET
| | | +--- LC81 SRAM_CE
| | | | +- LC83 SRAM_OE
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'F'
LC | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
Pin
30 -> * - - * - | - - - - - * - * | <-- DSP_A17
31 -> - * - * - | - - - - - * - * | <-- DSP_A18
47 -> - - - * - | - - - - - * - * | <-- DSP_DS
43 -> - - - * - | - - - - - * - * | <-- DSP_MSTRB
48 -> - - - * - | - - - - - * - * | <-- DSP_PS
44 -> - - - - * | - - - - - * * * | <-- DSP_R/W
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld1\c54.rpt
c54
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+----------------- LC99 FLASH_A14
| +--------------- LC101 FLASH_A15
| | +------------- LC110 FLASH_A16
| | | +----------- LC109 FLASH_BYTE
| | | | +--------- LC97 FLASH_WE
| | | | | +------- LC102 SRAM_A14
| | | | | | +----- LC104 SRAM_A15
| | | | | | | +--- LC105 SRAM_A16
| | | | | | | | +- LC107 SRAM_WE
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'G'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
51 -> * - - - - * - - - | - - - - - - * - | <-- DSP_A14
50 -> - * - - - - * - - | - - - - - - * * | <-- DSP_A15
29 -> - - * - - - - * - | - - - - - - * * | <-- DSP_A16
44 -> - - - - * - - - * | - - - - - * * * | <-- DSP_R/W
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\cpld1\c54.rpt
c54
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------- LC121 AD_CONVST
| +----------- LC123 AD_CS
| | +--------- LC128 AD_PD
| | | +------- LC125 AD_RD
| | | | +----- LC117 FLASH_CE
| | | | | +--- LC118 FLASH_OE
| | | | | | +- LC120 XBUS_ENA
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'H'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
Pin
77 -> * - * * - - - | * - - - - - - * | <-- DSP_A0
56 -> * - * * - - - | * - - - - - - * | <-- DSP_A1
57 -> * * * * - - - | * - - - - - - * | <-- DSP_A2
58 -> * * * * - - - | * - - - - - - * | <-- DSP_A3
50 -> - - - - * - - | - - - - - - * * | <-- DSP_A15
29 -> - - - - * - - | - - - - - - * * | <-- DSP_A16
30 -> - - - - * - - | - - - - - * - * | <-- DSP_A17
31 -> - - - - * - - | - - - - - * - * | <-- DSP_A18
47 -> - - - - * - - | - - - - - * - * | <-- DSP_DS
42 -> * * * * - - - | * - - - - - - * | <-- DSP_IOSTRB
46 -> * * * * - - * | * - - - - - - * | <-- DSP_IS
43 -> - - - - * - - | - - - - - * - * | <-- DSP_MSTRB
48 -> - - - - * - - | - - - - - * - * | <-- DSP_PS
44 -> - - - - - * - | - - - - - * * * | <-- DSP_R/W
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