📄 c54.rpt
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Project Information d:\cpld1\c54.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 10/21/2003 21:24:48
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
c54 EPM7128SQC100-10 35 41 0 41 0 32 %
User Pins: 35 41 0
Project Information d:\cpld1\c54.rpt
** PROJECT COMPILATION MESSAGES **
Design Doctor Warning: Logic that drives primitive 'DA_CS' contains a static 0 hazard when 'DSP_IOSTRB' = 0, 'DSP_IS' = 0, 'DSP_A3' = 1, 'DSP_A2' = 0, 'DSP_A1' = 0 and primitive 'DSP_A0' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'AD_CS' contains a static 0 hazard when 'DSP_IOSTRB' = 0, 'DSP_IS' = 0, 'DSP_A3' = 0, 'DSP_A2' = 1, 'DSP_A1' = 0 and primitive 'DSP_A0' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'AD_CS' contains a static 0 hazard when 'DSP_IOSTRB' = 0, 'DSP_IS' = 0, 'DSP_A3' = 0, 'DSP_A2' = 1, 'DSP_A0' = 0 and primitive 'DSP_A1' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'AD_CS' contains a static 0 hazard when 'DSP_IOSTRB' = 0, 'DSP_IS' = 0, 'DSP_A3' = 0, 'DSP_A2' = 1, 'DSP_A0' = 1 and primitive 'DSP_A1' changes -- hazard found before logic synthesis
Design Doctor Warning: Logic that drives primitive 'AD_CS' contains a static 0 hazard when 'DSP_IOSTRB' = 0, 'DSP_IS' = 0, 'DSP_A3' = 0, 'DSP_A2' = 1, 'DSP_A1' = 1 and primitive 'DSP_A0' changes -- hazard found before logic synthesis
Warning: Primitive 'IO4' is stuck at GND
Warning: Primitive 'IO2' is stuck at GND
Warning: Primitive 'IO1' is stuck at GND
Warning: Primitive 'CODEC_FC' is stuck at GND
Warning: Primitive 'FLASH_BYTE' is stuck at VCC
Warning: Primitive 'FLASH_RESET' is stuck at VCC
Warning: Primitive 'DSP_NMI' is stuck at VCC
Warning: Primitive 'DSP_INT1' is stuck at VCC
Warning: Primitive 'LED3' is stuck at VCC
Warning: Primitive 'DSP_BIO' is stuck at VCC
Warning: Primitive 'DSP_READY' is stuck at VCC
Warning: Primitive 'DSP_MP/MC' is stuck at VCC
Warning: Primitive 'DSP_INT0' is stuck at VCC
Info: Design Doctor issued 5 warning message(s) with EPLD Rules
Info: Reserved unused input pin 'PCI_HRST0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'CODEC_MCLK' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_CLKOUT' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_D0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_IAQ' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'FLASH_RY/BY' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_TOUT0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_MSC' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_ICAK' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_D7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_D6' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_D5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_D4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_D3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_D2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'DSP_D1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Information d:\cpld1\c54.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
c54@82 AD_CONVST
c54@83 AD_CS
c54@86 AD_EOC
c54@87 AD_PD
c54@85 AD_RD
c54@94 ALL_RESET
c54@99 CODEC_FC
c54@100 CODEC_MCLK
c54@98 CODEC_RESET
c54@95 DA_CS
c54@96 DA_WR
c54@77 DSP_A0
c54@56 DSP_A1
c54@57 DSP_A2
c54@58 DSP_A3
c54@51 DSP_A14
c54@50 DSP_A15
c54@29 DSP_A16
c54@30 DSP_A17
c54@31 DSP_A18
c54@35 DSP_BIO
c54@19 DSP_CLKOUT
c54@47 DSP_DS
c54@21 DSP_D0
c54@23 DSP_D1
c54@24 DSP_D2
c54@25 DSP_D3
c54@26 DSP_D4
c54@27 DSP_D5
c54@33 DSP_D6
c54@32 DSP_D7
c54@37 DSP_IAQ
c54@22 DSP_ICAK
c54@12 DSP_INT0
c54@14 DSP_INT1
c54@15 DSP_INT2
c54@16 DSP_INT3
c54@42 DSP_IOSTRB
c54@46 DSP_IS
c54@34 DSP_MP/MC
c54@39 DSP_MSC
c54@43 DSP_MSTRB
c54@11 DSP_NMI
c54@48 DSP_PS
c54@49 DSP_READY
c54@10 DSP_RS
c54@44 DSP_R/W
c54@18 DSP_TOUT0
c54@38 DSP_XF
c54@66 FLASH_A14
c54@67 FLASH_A15
c54@74 FLASH_A16
c54@59 FLASH_A17
c54@60 FLASH_A18
c54@73 FLASH_BYTE
c54@79 FLASH_CE
c54@80 FLASH_OE
c54@63 FLASH_RESET
c54@62 FLASH_RY/BY
c54@65 FLASH_WE
c54@4 IO1
c54@7 IO2
c54@8 IO3
c54@9 IO4
c54@1 LED1
c54@2 LED2
c54@3 LED3
c54@52 PCI_HINT0
c54@78 PCI_HRST0
c54@69 SRAM_A14
c54@70 SRAM_A15
c54@71 SRAM_A16
c54@54 SRAM_CE
c54@55 SRAM_OE
c54@72 SRAM_WE
c54@81 XBUS_ENA
Project Information d:\cpld1\c54.rpt
** FILE HIERARCHY **
|74154:139|
Device-Specific Information: d:\cpld1\c54.rpt
c54
***** Logic for device 'c54' compiled without errors.
Device: EPM7128SQC100-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = ON
Device-Specific Information: d:\cpld1\c54.rpt
c54
** ERROR SUMMARY **
Info: Chip 'c54' in device 'EPM7128SQC100-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
C
C O
O D A A
D C E L D X
E O C L _ B
C D _ _ V A C U
_ E R D D R C A D A V A O S
M C E A A E C D _ D C D N _
C _ S G _ _ S I G G G G G _ E _ C _ V E
L F E N W C E N N N N N N P O R I C S N
K C T D R S T T D D D D D D C D O S T A
------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 |_
/ 99 97 95 93 91 89 87 85 83 81 |
LED1 | 1 80 | FLASH_OE
LED2 | 2 79 | FLASH_CE
LED3 | 3 78 | PCI_HRST0
IO1 | 4 77 | DSP_A0
VCCIO | 5 76 | GND
#TDI | 6 75 | #TDO
IO2 | 7 74 | FLASH_A16
IO3 | 8 73 | FLASH_BYTE
IO4 | 9 72 | SRAM_WE
DSP_RS | 10 71 | SRAM_A16
DSP_NMI | 11 70 | SRAM_A15
DSP_INT0 | 12 69 | SRAM_A14
GND | 13 68 | VCCIO
DSP_INT1 | 14 67 | FLASH_A15
DSP_INT2 | 15 66 | FLASH_A14
DSP_INT3 | 16 EPM7128SQC100-10 65 | FLASH_WE
#TMS | 17 64 | #TCK
DSP_TOUT0 | 18 63 | FLASH_RESET
DSP_CLKOUT | 19 62 | FLASH_RY/BY
VCCIO | 20 61 | GND
DSP_D0 | 21 60 | FLASH_A18
DSP_ICAK | 22 59 | FLASH_A17
DSP_D1 | 23 58 | DSP_A3
DSP_D2 | 24 57 | DSP_A2
DSP_D3 | 25 56 | DSP_A1
DSP_D4 | 26 55 | SRAM_OE
DSP_D5 | 27 54 | SRAM_CE
GND | 28 53 | VCCIO
DSP_A16 | 29 52 | PCI_HINT0
DSP_A17 | 30 51 | DSP_A14
| 32 34 36 38 40 42 44 46 48 50 _|
\ 31 33 35 37 39 41 43 45 47 49 |
\-------------------------------------------
D D D D D V D D D G V D D D G D D D D D
S S S S S C S S S N C S S S N S S S S S
P P P P P C P P P D C P P P D P P P P P
_ _ _ _ _ I _ _ _ I _ _ _ _ _ _ _ _
A D D M B O I X M N I M R I D P R A
1 7 6 P I A F S T O S / S S S E 1
8 / O Q C S T W A 5
M T R D
C R B Y
B
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\cpld1\c54.rpt
c54
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 8/16( 50%) 10/10(100%) 0/16( 0%) 8/36( 22%)
B: LC17 - LC32 9/16( 56%) 10/10(100%) 0/16( 0%) 4/36( 11%)
C: LC33 - LC48 0/16( 0%) 10/10(100%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 2/16( 12%) 10/10(100%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 1/16( 6%) 10/10(100%) 0/16( 0%) 0/36( 0%)
F: LC81 - LC96 5/16( 31%) 10/10(100%) 0/16( 0%) 6/36( 16%)
G: LC97 - LC112 9/16( 56%) 10/10(100%) 0/16( 0%) 4/36( 11%)
H: LC113 - LC128 7/16( 43%) 10/10(100%) 0/16( 0%) 14/36( 38%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 80/80 (100%)
Total logic cells used: 41/128 ( 32%)
Total shareable expanders used: 0/128 ( 0%)
Total Turbo logic cells used: 41/128 ( 32%)
Total shareable expanders not available (n/a): 0/128 ( 0%)
Average fan-in: 1.70
Total fan-in: 70
Total input pins required: 35
Total fast input logic cells required: 0
Total output pins required: 41
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 41
Total flipflops required: 0
Total product terms required: 43
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: d:\cpld1\c54.rpt
c54
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