📄 e_clock.txt
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--*********************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sclk_run is
port(clk :in std_logic;
key1 :in std_logic;
key2 :in std_logic;
mode :in std_logic_vector(2 downto 0);
coun_shs1,coun_shs2 :inout std_logic_vector(3 downto 0) :="0000";
coun_ss1,coun_ss2 :inout std_logic_vector(3 downto 0) :="0000";
coun_sm1,coun_sm2 :inout std_logic_vector(3 downto 0) :="0000"
);
end sclk_run;
architecture Behavioral of sclk_run is
signal clk100hz :std_logic :='0';
signal clks :std_logic;
signal clkm :std_logic;
signal start :std_logic :='0';
signal counter :std_logic_vector(3 downto 0) :="0000";
signal key1s,key2s,enclks,enclkm :std_logic;
signal Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8 :std_logic;
begin
keys_pro:process(clk,mode,key1,key2)
begin
if(clk='1'and clk'event)then
if(mode="010")then --输入信号同步--
Q1<=key1;
Q2<=Q1;
Q3<=key2;
Q4<=Q3;
Q5<=clks;
Q6<=Q5;
Q7<=clkm;
Q8<=Q7;
end if;
key1s<=Q1 and not Q2;
key2s<=Q3 and not Q4;
enclks<=Q5 and not Q6;
enclkm<=Q7 and not Q8;
end if;
end process;
div_clkpro:process(clk,mode,key1s)
begin
if(clk='1'and clk'event)then
if(mode="010")then
if(counter>="1001")then
counter<="0000";
clk100hz<='1';
else
counter<=counter+'1';
clk100hz<='0';
end if;
end if;
if(key1s='1')then
start<=not start;
end if;
else
end if;
end process;
sclkrun_pro:process(clk,clk100hz,key1s,key2s,start,clks,clkm)
begin
if(clk='1'and clk'event)then
if(key2s='1'and start='0') then
coun_shs2 <="0000";
coun_shs1 <="0000";
coun_ss2 <="0000";
coun_ss1 <="0000";
coun_sm2 <="0000";
coun_sm1 <="0000";
elsif(start='1')then
if(clk100hz='1')then
if(coun_shs2="1001"and coun_shs1="1001")then
coun_shs2<="0000";
coun_shs1<="0000";
clks<='1';
elsif(coun_shs2="1001")then
coun_shs2<="0000";
coun_shs1<=coun_shs1+'1';
clks<='0';
else
coun_shs1<=coun_shs1;
coun_shs2<=coun_shs2+'1';
clks<='0';
end if;
end if;
if(enclks='1')then
if(coun_ss2="1001"and coun_ss1="1001")then
coun_ss2<="0000";
coun_ss1<="0000";
clkm<='1';
elsif(coun_ss2="1001")then
coun_ss2<="0000";
coun_ss1<=coun_ss1+'1';
clkm<='0';
else
coun_ss1<=coun_ss1;
coun_ss2<=coun_ss2+'1';
clkm<='0';
end if;
end if;
if(enclkm='1')then
if(coun_sm2="1001"and coun_sm1="1001")then
coun_sm2<="0000";
coun_sm1<="0000";
elsif(coun_sm2="1001")then
coun_sm2<="0000";
coun_sm1<=coun_sm1+'1';
else
coun_sm1<=coun_sm1;
coun_sm2<=coun_sm2+'1';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
--*********************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alarm_set is
port(clk,key1,key2 :in std_logic;
mode :in std_logic_vector(2 downto 0);
set_m2,set_m1 :inout std_logic_vector(3 downto 0):="0010";
set_h2 :inout std_logic_vector(3 downto 0):="0010";
set_h1 :inout std_logic_vector(1 downto 0):="10"
);
end alarm_set;
architecture Behavioral of alarm_set is
signal key1a,key2a :std_logic;
signal Q1,Q2,Q3,Q4 :std_logic;
begin
keya_pro:process(clk,mode,key1,key2)
begin
if(clk='1'and clk'event)then
if(mode="011")then --输入信号同步--
Q1<=key1;
Q2<=Q1;
Q3<=key2;
Q4<=Q3;
end if;
key1a<=Q1 and not Q2;
key2a<=Q3 and not Q4;
end if;
end process;
set_pro:process(clk,mode,key1a,key2a)
begin
if(clk='1'and clk'event)then
if(mode="011")then
if(key1a='1')then
if(set_m2="1001"and set_m1="0101")then
set_m2<="0000";
set_m1<="0000";
elsif(set_m2="1001")then
set_m2<="0000";
set_m1<=set_m1+'1';
else
set_m2<=set_m2+'1';
set_m1<=set_m1;
end if;
end if;
if(key2a='1')then
if(set_h2="0011"and set_h1="0010")then
set_h2<="0000";
set_h1<="00";
elsif(set_m2="1001")then
set_h2<="0000";
set_h1<=set_h1+'1';
else
set_h2<=set_h2+'1';
set_h1<=set_h1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
--*********************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity date is
port(clk,key1,key2 :in std_logic;
mode :in std_logic_vector(2 downto 0);
clkd :in std_logic;
coun_dm2,coun_dd1 :inout std_logic_vector(3 downto 0) :="0000";
coun_dm1 :inout std_logic_vector(1 downto 0) :="01";
coun_dd2 :inout std_logic_vector(3 downto 0) :="0001"
);
end date;
architecture Behavioral of date is
signal month :std_logic_vector(5 downto 0);
signal key1d,key2d,clkm,enclkd,enclkm :std_logic :='0';
signal Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8 :std_logic :='0';
begin
month<=coun_dm1&coun_dm2;
keyd_pro:process(clk,mode,key1,key2,clkd,clkm)
begin
if(clk='1'and clk'event)then
if(mode="100")then --输入信号同步--
Q1<=key1;
Q2<=Q1;
Q3<=key2;
Q4<=Q3;
else
Q5<=clkd;
Q6<=Q5;
Q7<=clkm;
Q8<=Q7;
end if;
key1d<=Q1 and not Q2;
key2d<=Q3 and not Q4;
enclkd<=Q5 and not Q6;
enclkm<=Q7 and not Q8;
end if;
end process;
date_run:process(clk,mode,enclkd,enclkm,key1d,key2d)
begin
if(clk='1'and clk'event)then
if(mode/="100")then
if(enclkd='1')then
case month is
when "000001"|"000011"|"000101"|"000111"|
"001000"|"010000"|"010010" =>
if(coun_dd1="0011"and coun_dd2="0001")then
coun_dd2<="0001";
coun_dd1<="0000";
clkm<='1';
elsif(coun_dd2="1001")then
coun_dd2<="0000";
coun_dd1<=coun_dd1+'1';
clkm<='0';
else
coun_dd2<=coun_dd2+'1';
coun_dd1<=coun_dd1;
clkm<='0';
end if;
when "000100"|"000110"|"001001"|"010001" =>
if(coun_dd1="0011"and coun_dd2="0001")then
coun_dd2<="0001";
coun_dd1<="0000";
clkm<='1';
elsif(coun_dd2="1001")then
coun_dd2<="0000";
coun_dd1<=coun_dd1+'1';
clkm<='0';
else
coun_dd2<=coun_dd2+'1';
coun_dd1<=coun_dd1;
clkm<='0';
end if;
when "000010" =>
if(coun_dd1="0010"and coun_dd2="1000")then
coun_dd2<="0001";
coun_dd1<="0000";
clkm<='1';
elsif(coun_dd2="1001")then
coun_dd2<="0000";
coun_dd1<=coun_dd1+'1';
clkm<='0';
else
coun_dd2<=coun_dd2+'1';
coun_dd1<=coun_dd1;
clkm<='0';
end if;
when others =>null;
end case;
end if;
if(enclkm='1')then
if(coun_dm1="01"and coun_dm2="0010")then
coun_dm2<="0001";
coun_dm1<="00";
elsif(coun_dm2="1001")then
coun_dm2<="0000";
coun_dm1<=coun_dm1+'1';
else
coun_dm2<=coun_dm2+'1';
coun_dm1<=coun_dm1;
end if;
end if;
else
if(key1d='1')then
case month is
when "000001"|"000011"|"000101"|"000111"|
"001000"|"010000"|"010010" =>
if(coun_dd1="0011"and coun_dd2="0001")then
coun_dd2<="0001";
coun_dd1<="0000";
elsif(coun_dd2="1001")then
coun_dd2<="0000";
coun_dd1<=coun_dd1+'1';
else
coun_dd2<=coun_dd2+'1';
coun_dd1<=coun_dd1;
end if;
when "000100"|"000110"|"001001"|"010001" =>
if(coun_dd1="0011"and coun_dd2="0000")then
coun_dd2<="0001";
coun_dd1<="0000";
elsif(coun_dd2="1001")then
coun_dd2<="0000";
coun_dd1<=coun_dd1+'1';
else
coun_dd2<=coun_dd2+'1';
coun_dd1<=coun_dd1;
end if;
when "000010" =>
if(coun_dd1="0010"and coun_dd2="1000")then
coun_dd2<="0001";
coun_dd1<="0000";
elsif(coun_dd2="1001")then
coun_dd2<="0000";
coun_dd1<=coun_dd1+'1';
else
coun_dd2<=coun_dd2+'1';
coun_dd1<=coun_dd1;
end if;
when others =>null;
end case;
end if;
if(key2d='1')then
if(coun_dm1="01"and coun_dm2="0010")then
coun_dm2<="0001";
coun_dm1<="00";
elsif(coun_dm2="1001")then
coun_dm2<="0000";
coun_dm1<=coun_dm1+'1';
else
coun_dm2<=coun_dm2+'1';
coun_dm1<=coun_dm1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
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