📄 2_05_12g.lst
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C51 COMPILER V6.10 2_05_12G 04/09/2001 14:58:54 PAGE 1
C51 COMPILER V6.10, COMPILATION OF MODULE 2_05_12G
OBJECT MODULE PLACED IN .\2_05_12G.OBJ
COMPILER INVOKED BY: C:\KEIL\C51\BIN\C51.EXE .\2_05_12G.C OPTIMIZE(6,SPEED) BROWSE DEBUG OBJECTEXTEND CODE LISTINCLUDE S
-YMBOLS
stmt level source
1 /*------------------------------------------------------------------*-
2
3 2_05_12g.C (v1.00)
4
5 ------------------------------------------------------------------
6
7 *** THIS IS A SCHEDULER FOR STANDARD 8051 / 8052 ***
8
9 *** Uses T2 for timing, 16-bit auto reload ***
10 *** 12 MHz oscillator -> 5 ms (precise) tick interval ***
11
12
13 COPYRIGHT
14 ---------
15
16 This code is from the book:
17
18 PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont
19 [Pearson Education, 2001; ISBN: 0-201-33138-1].
20
21 This code is copyright (c) 2001 by Michael J. Pont.
22
23 See book for copyright details and other information.
24
25 -*------------------------------------------------------------------*/
26
27 #include "2_05_12g.h"
1 =1 /*------------------------------------------------------------------*-
2 =1
3 =1 2_05_12g.h (v1.00)
4 =1
5 =1 ------------------------------------------------------------------
6 =1
7 =1 - see 2_05_12g.C for details
8 =1
9 =1
10 =1 COPYRIGHT
11 =1 ---------
12 =1
13 =1 This code is from the book:
14 =1
15 =1 PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont
16 =1 [Pearson Education, 2001; ISBN: 0-201-33138-1].
17 =1
18 =1 This code is copyright (c) 2001 by Michael J. Pont.
19 =1
20 =1 See book for copyright details and other information.
21 =1
22 =1 -*------------------------------------------------------------------*/
23 =1
24 =1 #include "Main.h"
1 =2 /*------------------------------------------------------------------*-
2 =2
3 =2 Main.H (v1.00)
C51 COMPILER V6.10 2_05_12G 04/09/2001 14:58:54 PAGE 2
4 =2
5 =2 ------------------------------------------------------------------
6 =2
7 =2 'Project Header' (see Chap 9) for project 255_TICK (see Chap 37)
8 =2
9 =2
10 =2 COPYRIGHT
11 =2 ---------
12 =2
13 =2 This code is from the book:
14 =2
15 =2 PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont
16 =2 [Pearson Education, 2001; ISBN: 0-201-33138-1].
17 =2
18 =2 This code is copyright (c) 2001 by Michael J. Pont.
19 =2
20 =2 See book for copyright details and other information.
21 =2
22 =2 -*------------------------------------------------------------------*/
23 =2
24 =2 #ifndef _MAIN_H
25 =2 #define _MAIN_H
26 =2
27 =2 //------------------------------------------------------------------
28 =2 // WILL NEED TO EDIT THIS SECTION FOR EVERY PROJECT
29 =2 //------------------------------------------------------------------
30 =2
31 =2 // Must include the appropriate microcontroller header file here
32 =2 #include <AT89x52.h>
1 =3 /*--------------------------------------------------------------------------
2 =3 AT89X52.H
3 =3
4 =3 Header file for the low voltage Flash Atmel AT89C52 and AT89LV52.
5 =3 Copyright (c) 1995-1996 Keil Software, Inc. All rights reserved.
6 =3 --------------------------------------------------------------------------*/
7 =3
8 =3 #ifndef AT89X52_HEADER_FILE
9 =3 #define AT89X52_HEADER_FILE 1
10 =3
11 =3 /*------------------------------------------------
12 =3 Byte Registers
13 =3 ------------------------------------------------*/
14 =3 sfr P0 = 0x80;
15 =3 sfr SP = 0x81;
16 =3 sfr DPL = 0x82;
17 =3 sfr DPH = 0x83;
18 =3 sfr PCON = 0x87;
19 =3 sfr TCON = 0x88;
20 =3 sfr TMOD = 0x89;
21 =3 sfr TL0 = 0x8A;
22 =3 sfr TL1 = 0x8B;
23 =3 sfr TH0 = 0x8C;
24 =3 sfr TH1 = 0x8D;
25 =3 sfr P1 = 0x90;
26 =3 sfr SCON = 0x98;
27 =3 sfr SBUF = 0x99;
28 =3 sfr P2 = 0xA0;
29 =3 sfr IE = 0xA8;
30 =3 sfr P3 = 0xB0;
31 =3 sfr IP = 0xB8;
32 =3 sfr T2CON = 0xC8;
33 =3 sfr T2MOD = 0xC9;
C51 COMPILER V6.10 2_05_12G 04/09/2001 14:58:54 PAGE 3
34 =3 sfr RCAP2L = 0xCA;
35 =3 sfr RCAP2H = 0xCB;
36 =3 sfr TL2 = 0xCC;
37 =3 sfr TH2 = 0xCD;
38 =3 sfr PSW = 0xD0;
39 =3 sfr ACC = 0xE0;
40 =3 sfr B = 0xF0;
41 =3
42 =3 /*------------------------------------------------
43 =3 P0 Bit Registers
44 =3 ------------------------------------------------*/
45 =3 sbit P0_0 = 0x80;
46 =3 sbit P0_1 = 0x81;
47 =3 sbit P0_2 = 0x82;
48 =3 sbit P0_3 = 0x83;
49 =3 sbit P0_4 = 0x84;
50 =3 sbit P0_5 = 0x85;
51 =3 sbit P0_6 = 0x86;
52 =3 sbit P0_7 = 0x87;
53 =3
54 =3 /*------------------------------------------------
55 =3 PCON Bit Values
56 =3 ------------------------------------------------*/
57 =3 #define IDL_ 0x01
58 =3
59 =3 #define STOP_ 0x02
60 =3 #define PD_ 0x02 /* Alternate definition */
61 =3
62 =3 #define GF0_ 0x04
63 =3 #define GF1_ 0x08
64 =3 #define SMOD_ 0x80
65 =3
66 =3 /*------------------------------------------------
67 =3 TCON Bit Registers
68 =3 ------------------------------------------------*/
69 =3 sbit IT0 = 0x88;
70 =3 sbit IE0 = 0x89;
71 =3 sbit IT1 = 0x8A;
72 =3 sbit IE1 = 0x8B;
73 =3 sbit TR0 = 0x8C;
74 =3 sbit TF0 = 0x8D;
75 =3 sbit TR1 = 0x8E;
76 =3 sbit TF1 = 0x8F;
77 =3
78 =3 /*------------------------------------------------
79 =3 TMOD Bit Values
80 =3 ------------------------------------------------*/
81 =3 #define T0_M0_ 0x01
82 =3 #define T0_M1_ 0x02
83 =3 #define T0_CT_ 0x04
84 =3 #define T0_GATE_ 0x08
85 =3 #define T1_M0_ 0x10
86 =3 #define T1_M1_ 0x20
87 =3 #define T1_CT_ 0x40
88 =3 #define T1_GATE_ 0x80
89 =3
90 =3 #define T1_MASK_ 0xF0
91 =3 #define T0_MASK_ 0x0F
92 =3
93 =3 /*------------------------------------------------
94 =3 P1 Bit Registers
95 =3 ------------------------------------------------*/
C51 COMPILER V6.10 2_05_12G 04/09/2001 14:58:54 PAGE 4
96 =3 sbit P1_0 = 0x90;
97 =3 sbit P1_1 = 0x91;
98 =3 sbit P1_2 = 0x92;
99 =3 sbit P1_3 = 0x93;
100 =3 sbit P1_4 = 0x94;
101 =3 sbit P1_5 = 0x95;
102 =3 sbit P1_6 = 0x96;
103 =3 sbit P1_7 = 0x97;
104 =3
105 =3 sbit T2 = 0x90; /* External input to Timer/Counter 2, clock out */
106 =3 sbit T2EX = 0x91; /* Timer/Counter 2 capture/reload trigger & dir ctl */
107 =3
108 =3 /*------------------------------------------------
109 =3 SCON Bit Registers
110 =3 ------------------------------------------------*/
111 =3 sbit RI = 0x98;
112 =3 sbit TI = 0x99;
113 =3 sbit RB8 = 0x9A;
114 =3 sbit TB8 = 0x9B;
115 =3 sbit REN = 0x9C;
116 =3 sbit SM2 = 0x9D;
117 =3 sbit SM1 = 0x9E;
118 =3 sbit SM0 = 0x9F;
119 =3
120 =3 /*------------------------------------------------
121 =3 P2 Bit Registers
122 =3 ------------------------------------------------*/
123 =3 sbit P2_0 = 0xA0;
124 =3 sbit P2_1 = 0xA1;
125 =3 sbit P2_2 = 0xA2;
126 =3 sbit P2_3 = 0xA3;
127 =3 sbit P2_4 = 0xA4;
128 =3 sbit P2_5 = 0xA5;
129 =3 sbit P2_6 = 0xA6;
130 =3 sbit P2_7 = 0xA7;
131 =3
132 =3 /*------------------------------------------------
133 =3 IE Bit Registers
134 =3 ------------------------------------------------*/
135 =3 sbit EX0 = 0xA8; /* 1=Enable External interrupt 0 */
136 =3 sbit ET0 = 0xA9; /* 1=Enable Timer 0 interrupt */
137 =3 sbit EX1 = 0xAA; /* 1=Enable External interrupt 1 */
138 =3 sbit ET1 = 0xAB; /* 1=Enable Timer 1 interrupt */
139 =3 sbit ES = 0xAC; /* 1=Enable Serial port interrupt */
140 =3 sbit ET2 = 0xAD; /* 1=Enable Timer 2 interrupt */
141 =3
142 =3 sbit EA = 0xAF; /* 0=Disable all interrupts */
143 =3
144 =3 /*------------------------------------------------
145 =3 P3 Bit Registers (Mnemonics & Ports)
146 =3 ------------------------------------------------*/
147 =3 sbit P3_0 = 0xB0;
148 =3 sbit P3_1 = 0xB1;
149 =3 sbit P3_2 = 0xB2;
150 =3 sbit P3_3 = 0xB3;
151 =3 sbit P3_4 = 0xB4;
152 =3 sbit P3_5 = 0xB5;
153 =3 sbit P3_6 = 0xB6;
154 =3 sbit P3_7 = 0xB7;
155 =3
156 =3 sbit RXD = 0xB0; /* Serial data input */
157 =3 sbit TXD = 0xB1; /* Serial data output */
C51 COMPILER V6.10 2_05_12G 04/09/2001 14:58:54 PAGE 5
158 =3 sbit INT0 = 0xB2; /* External interrupt 0 */
159 =3 sbit INT1 = 0xB3; /* External interrupt 1 */
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