📄 scc_m515.lst
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37 =1
38 =1 // Control Register
39 =1 #define CAN_cr (*((tByte volatile xdata *) 0xF700))
40 =1
41 =1 // Status Register
42 =1 #define CAN_sr (*((tByte volatile xdata *) 0xF701))
43 =1
44 =1 // Bit Timing Register
45 =1 #define CAN_btr0 (*((tByte volatile xdata *) 0xF704))
46 =1 #define CAN_btr1 (*((tByte volatile xdata *) 0xF705))
47 =1
C51 COMPILER V6.10 SCC_M515 04/19/2001 14:10:31 PAGE 15
48 =1 // Global Mask Short
49 =1 #define CAN_gms0 (*((tByte volatile xdata *) 0xF706))
50 =1
51 =1 // Global Mask Short
52 =1 #define CAN_gms1 (*((tByte volatile xdata *) 0xF707))
53 =1
54 =1 // Upper Global Mask Long
55 =1 #define CAN_ugml0 (*((tByte volatile xdata *) 0xF708))
56 =1 #define CAN_ugml1 (*((tByte volatile xdata *) 0xF709))
57 =1
58 =1 // Lower Global Mask Long
59 =1 #define CAN_lgml0 (*((tByte volatile xdata *) 0xF70A))
60 =1 #define CAN_lgml1 (*((tByte volatile xdata *) 0xF70B))
61 =1
62 =1 // ------ Private data type declarations ---------------------------
63 =1
64 =1 // Data structure representing a single CAN message
65 =1 struct sCAN_message
66 =1 {
67 =1 tByte MCR0; // Message Control Register 0
68 =1 tByte MCR1; // Message Control Register 1
69 =1 tByte UAR0; // Upper Arbit. Reg. 0
70 =1 tByte UAR1; // Upper Arbit. Reg. 1
71 =1 tByte LAR0; // Lower Arbit. Reg. 0
72 =1 tByte LAR1; // Lower Arbit. Reg. 1
73 =1 tByte MCFG; // Message Configuration Register
74 =1 tByte Data[8]; // Message Data 0 .. 7
75 =1 tByte Customer; // Reserved for application specific data
76 =1 };
77 =1
78 =1 // ------ Private variables ----------------------------------------
79 =1
80 =1 // A total of 15 CAN message structures exist
81 =1 // (starting at at address 0xF710)
82 =1 #define CAN_messages ((struct sCAN_message volatile xdata *) 0xF710)
83 =1
84 =1 /*------------------------------------------------------------------*-
85 =1 ---- END OF FILE -------------------------------------------------
86 =1 -*------------------------------------------------------------------*/
87 =1
44
45 // ------ Public variable definitions ------------------------------
46
47 // Four bytes of data (plus ID information) are sent
48 tByte Tick_message_data_G[NUMBER_OF_SLAVES][4] = {'M'};
49 tByte Ack_message_data_G[NUMBER_OF_SLAVES][4];
50
51 // ------ Public variable declarations -----------------------------
52
53 // The array of tasks (see Sch51.c)
54 extern sTask SCH_tasks_G[SCH_MAX_TASKS];
55
56 // The error code variable (see Sch51.c)
57 extern tByte Error_code_G;
58
59 // ------ Private variable definitions -----------------------------
60
61 static tByte Slave_index_G = 0;
62 static bit First_ack_G = 1;
63
64 // ------ Private function prototypes ------------------------------
65
C51 COMPILER V6.10 SCC_M515 04/19/2001 14:10:31 PAGE 16
66 static void SCC_A_MASTER_Send_Tick_Message(const tByte);
67 static bit SCC_A_MASTER_Process_Ack(const tByte);
68
69 static void SCC_A_MASTER_Shut_Down_the_Network(void);
70
71 static void SCC_A_MASTER_Enter_Safe_State(void);
72
73 static void SCC_A_MASTER_Watchdog_Init(void);
74 static void SCC_A_MASTER_Watchdog_Refresh(void) reentrant;
75
76 static tByte SCC_A_MASTER_Start_Slave(const tByte) reentrant;
77
78
79 // ------ Private constants ----------------------------------------
80
81 // Do not use ID 0x00 (used to start slaves)
82 static const tByte MAIN_SLAVE_IDs[NUMBER_OF_SLAVES] = {0x01};
83 static const tByte BACKUP_SLAVE_IDs[NUMBER_OF_SLAVES] = {0x02};
84
85 #define NO_NETWORK_ERROR (1)
86 #define NETWORK_ERROR (0)
87
88 // ------ Private variables ----------------------------------------
89
90 static tWord Slave_reset_attempts_G[NUMBER_OF_SLAVES];
91
92 // Slave IDs may be any non-zero tByte value (but all must be different)
93 static tByte Current_Slave_IDs_G[NUMBER_OF_SLAVES] = {0};
94
95
96 /*------------------------------------------------------------------*-
97
98 SCC_A_MASTER_Init_T2_CAN()
99
100 Scheduler initialisation function. Prepares scheduler data
101 structures and sets up timer interrupts at required rate.
102 Must call this function before using the scheduler.
103
104 -*------------------------------------------------------------------*/
105 void SCC_A_MASTER_Init_T2_CAN(void)
106 {
107 1 tByte i;
108 1 tByte Message;
109 1 tByte Slave_index;
110 1
111 1 // No interrupts (yet)
112 1 EAL = 0;
113 1
114 1 // Start the watchdog
115 1 SCC_A_MASTER_Watchdog_Init();
116 1
117 1 Network_error_pin = NO_NETWORK_ERROR;
118 1
119 1 // ------ Set up the scheduler ----------------------------------
120 1 // Sort out the tasks
121 1 for (i = 0; i < SCH_MAX_TASKS; i++)
122 1 {
123 2 SCH_Delete_Task(i);
124 2 }
125 1
126 1 // Reset the global error variable
127 1 // - SCH_Delete_Task() will generate an error code,
C51 COMPILER V6.10 SCC_M515 04/19/2001 14:10:31 PAGE 17
128 1 // (because the task array is empty)
129 1 Error_code_G = 0;
130 1
131 1 // We allow any combination of ID numbers in slaves
132 1 for (Slave_index = 0; Slave_index < NUMBER_OF_SLAVES; Slave_index++)
133 1 {
134 2 Slave_reset_attempts_G[Slave_index] = 0;
135 2 Current_Slave_IDs_G[Slave_index] = MAIN_SLAVE_IDs[Slave_index];
136 2 }
137 1
138 1 // Get ready to send first tick message
139 1 First_ack_G = 1;
140 1 Slave_index_G = 0;
141 1
142 1 // ------ Set up the CAN link (begin) ------------------------
143 1
144 1 // ---------------- SYSCON Register --------------
145 1 // The access to XRAM and CAN controller is enabled.
146 1 // The signals !RD and !WR are not activated during accesses
147 1 // to the XRAM/CAN controller.
148 1 // ALE generation is enabled.
149 1 SYSCON = 0x20;
150 1
151 1 // ------------ CAN Control/Status Register --------------
152 1 // Start to init the CAN module
153 1 CAN_cr = 0x41; // INIT and CCE
154 1
155 1 // ------------ Bit Timing Register ---------------------
156 1 // Baudrate = 333.333 kbaud
157 1 // - Need 308+ kbaud plus for 1ms ticks, 8 data bytes
158 1 // - See text for details
159 1 //
160 1 // There are 5 time quanta before sample point
161 1 // There are 4 time quanta after sample point
162 1 // The (re)synchronization jump width is 2 time quanta
163 1 CAN_btr1 = 0x34; // Bit Timing Register
164 1 CAN_btr0 = 0x42;
165 1
166 1 CAN_gms1 = 0xFF; // Global Mask Short Register 1
167 1 CAN_gms0 = 0xFF; // Global Mask Short Register 0
168 1
169 1 CAN_ugml1 = 0xFF; // Upper Global Mask Long Register 1
170 1 CAN_ugml0 = 0xFF; // Upper Global Mask Long Register 0
171 1
172 1 CAN_lgml1 = 0xF8; // Lower Global Mask Long Register 1
173 1 CAN_lgml0 = 0xFF; // Lower Global Mask Long Register 0
174 1
175 1 // --- Configure the 'Tick' Message Object ---
176 1 // 'Message Object 1' is valid
177 1 CAN_messages[0].MCR1 = 0x55; // Message Control Register 1
178 1 CAN_messages[0].MCR0 = 0x95; // Message Control Register 0
179 1
180 1 // Message direction is transmit
181 1 // Extended 29-bit identifier
182 1 // These have ID 0x000000 and 5 valid data bytes
183 1 CAN_messages[0].MCFG = 0x5C; // Message Configuration Register
184 1
185 1 CAN_messages[0].UAR1 = 0x00; // Upper Arbit. Reg. 1
186 1 CAN_messages[0].UAR0 = 0x00; // Upper Arbit. Reg. 0
187 1 CAN_messages[0].LAR1 = 0x00; // Lower Arbit. Reg. 1
188 1 CAN_messages[0].LAR0 = 0x00; // Lower Arbit. Reg. 0
189 1
C51 COMPILER V6.10 SCC_M515 04/19/2001 14:10:31 PAGE 18
190 1 CAN_messages[0].Data[0] = 0x00; // data byte 0
191 1 CAN_messages[0].Data[1] = 0x00; // data byte 1
192 1 CAN_messages[0].Data[2] = 0x00; // data byte 2
193 1 CAN_messages[0].Data[3] = 0x00; // data byte 3
194 1 CAN_messages[0].Data[4] = 0x00; // data byte 4
195 1
196 1 // --- Configure the 'Ack' Message Object ---
197 1
198 1 // 'Message Object 2' is valid
199 1 // NOTE: Object 2 receives *ALL* ack messages
200 1 CAN_messages[1].MCR1 = 0x55; // Message Control Register 1
201 1 CAN_messages[1].MCR0 = 0x95; // Message Control Register 0
202 1
203 1 // Message direction is receive
204 1 // Extended 29-bit identifier
205 1 // These all have ID: 0x000000FF (5 valid data bytes)
206 1 CAN_messages[1].MCFG = 0x04; // Message Configuration Register
207 1
208 1 CAN_messages[1].UAR1 = 0x00; // Upper Arbit. Reg. 1
209 1 CAN_messages[1].UAR0 = 0x00; // Upper Arbit. Reg. 0
210 1 CAN_messages[1].LAR1 = 0xF8; // Lower Arbit. Reg. 1
211 1 CAN_messages[1].LAR0 = 0x07; // Lower Arbit. Reg. 0
212 1
213 1 // Configure remaining message objects - none are valid
214 1 for (Message = 2; Message <= 14; ++Message)
215 1 {
216 2 CAN_messages[Message].MCR1 = 0x55; // Message Control Register 1
217 2 CAN_messages[Message].MCR0 = 0x55; // Message Control Register 0
218 2 }
219 1
220 1 // ------------ CAN Control Register ---------------------
221 1 // reset CCE and INIT
222 1 CAN_cr = 0x00;
223 1
224 1 // ------ Set up the CAN link (end) --------------------------
225 1
226 1 // ------ Set up Timer 2 (begin) --------------------------------
227 1 // 80c515c, 10 MHz
228 1 // Timer 2 is set to overflow every 6 ms - see text
229 1 // Mode 1 = Timerfunction
230 1
231 1 // Prescaler: Fcpu/12
232 1 T2PS = 1;
233 1
234 1 // Mode 0 = auto-reload upon timer overflow
235 1 // Preset the timer register with autoreload value
236 1 // NOTE: Timing is same as standard (8052) T2 timing
237 1 // - if T2PS = 1 (otherwise twice as fast as 8052)
238 1 TL2 = 0x78;
239 1 TH2 = 0xEC;
240 1
241 1 // Mode 0 for all channels
242 1 T2CON |= 0x11;
243 1
244 1 // timer 2 overflow interrupt is enabled
245 1 ET2 = 1;
246 1 // timer 2 external reload interrupt is disabled
247 1 EXEN2 = 0;
248 1
249 1 // Compare/capture Channel 0
250 1 // Disabled
251 1 // Compare Register CRC on: 0x0000;
C51 COMPILER V6.10 SCC_M515 04/19/2001 14:10:31 PAGE 19
252 1 CRCL = 0x78;
253 1 CRCH = 0xEC;
254 1
255 1 // CC0/ext3 interrupt is disabled
256 1 EX3 = 0;
257 1
258 1 // Compare/capture Channel 1-3
259 1 // Disabled
260 1 CCL1 = 0x00;
261 1 CCH1 = 0x00;
262 1 CCL2 = 0x00;
263 1 CCH2 = 0x00;
264 1 CCL3 = 0x00;
265 1 CCH3 = 0x00;
266 1
267 1 // Interrupts Channel 1-3
268 1 // Disabled
269 1 EX4 = 0;
270 1 EX5 = 0;
271 1 EX6 = 0;
272 1
273 1 // all above mentioned modes for Channel 0 to Channel 3
274 1 CCEN = 0x00;
275 1 // ------ Set up Timer 2 (end) ----------------------------------
276 1 }
277
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