📄 scc_m515.lst
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C51 COMPILER V6.10 SCC_M515 04/19/2001 14:10:31 PAGE 1
C51 COMPILER V6.10, COMPILATION OF MODULE SCC_M515
OBJECT MODULE PLACED IN .\SCC_M515.OBJ
COMPILER INVOKED BY: C:\KEIL\C51\BIN\C51.EXE .\SCC_M515.C OPTIMIZE(6,SIZE) BROWSE DEBUG OBJECTEXTEND CODE LISTINCLUDE SY
-MBOLS
stmt level source
1 /*------------------------------------------------------------------*-
2
3 SCC_M515.c (v1.01)
4
5 ------------------------------------------------------------------
6
7 *** THIS IS A SHARED-CLOCK (CAN) SCHEDULER (MASTER) ***
8 *** FOR 80C515C (etc.) ***
9
10 *** Uses T2 for timing, 16-bit auto reload ***
11
12 *** This version assumes 10 MHz crystal on 515c ***
13 *** 6 ms (precise) tick interval ***
14
15 *** Both Master and Slave(s) share the same tick rate ***
16
17
18 -----------------------------------------------------------
19 --- NOTE: 'Idle mode' must be disabled (in Sch51.C) ---
20 --- or the on-chip watchdog will not function correctly ---
21 -----------------------------------------------------------
22
23
24 COPYRIGHT
25 ---------
26
27 This code is from the book:
28
29 PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont
30 [Pearson Education, 2001; ISBN: 0-201-33138-1].
31
32 This code is copyright (c) 2001 by Michael J. Pont.
33
34 See book for copyright details and other information.
35
36 -*------------------------------------------------------------------*/
37
38 #include "Main.h"
1 =1 /*------------------------------------------------------------------*-
2 =1
3 =1 Main.H (v1.00)
4 =1
5 =1 ------------------------------------------------------------------
6 =1
7 =1 'Project Header' (see Chap 9) for project SCU_Cb (see Chap 27)
8 =1
9 =1
10 =1 COPYRIGHT
11 =1 ---------
12 =1
13 =1 This code is from the book:
14 =1
15 =1 PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont
16 =1 [Pearson Education, 2001; ISBN: 0-201-33138-1].
C51 COMPILER V6.10 SCC_M515 04/19/2001 14:10:31 PAGE 2
17 =1
18 =1 This code is copyright (c) 2001 by Michael J. Pont.
19 =1
20 =1 See book for copyright details and other information.
21 =1
22 =1 -*------------------------------------------------------------------*/
23 =1
24 =1 #ifndef _MAIN_H
25 =1 #define _MAIN_H
26 =1
27 =1 //------------------------------------------------------------------
28 =1 // WILL NEED TO EDIT THIS SECTION FOR EVERY PROJECT
29 =1 //------------------------------------------------------------------
30 =1
31 =1 // Must include the appropriate microcontroller header file here
32 =1 #include <reg515c.h>
1 =2 /*------------------------------------------------------------------
2 =2 REG515C.H
3 =2
4 =2 Header file for the Infineon C515C
5 =2 Copyright (c) 1995-1999 Keil Elektronik GmbH All rights reserved.
6 =2 ------------------------------------------------------------------*/
7 =2
8 =2 /* BYTE Registers */
9 =2 /* CPU */
10 =2 sfr ACC = 0xE0;
11 =2 sfr B = 0xF0;
12 =2 sfr DPL = 0x82;
13 =2 sfr DPH = 0x83;
14 =2 sfr DPSEL = 0x92;
15 =2 sfr PSW = 0xD0;
16 =2 sfr SP = 0x81;
17 =2 sfr SYSCON = 0xB1;
18 =2
19 =2 /* A/D Converter */
20 =2 sfr ADCON0 = 0xD8;
21 =2 sfr ADDATH = 0xD9;
22 =2 sfr ADDATL = 0xDA; /* in mapped SFR area */
23 =2 sfr ADCON1 = 0xDC;
24 =2
25 =2 /* Interrupt System */
26 =2 sfr IEN0 = 0xA8;
27 =2 sfr IEN1 = 0xB8;
28 =2 sfr IEN2 = 0x9A;
29 =2 sfr IP0 = 0xA9;
30 =2 sfr IP1 = 0xB9;
31 =2 sfr IRCON = 0xC0;
32 =2
33 =2 /* XRAM */
34 =2 sfr XPAGE = 0x91;
35 =2
36 =2 /* Ports */
37 =2 sfr P0 = 0x80;
38 =2 sfr P1 = 0x90;
39 =2 sfr P2 = 0xA0;
40 =2 sfr P3 = 0xB0;
41 =2 sfr P4 = 0xE8;
42 =2 sfr P5 = 0xF8;
43 =2 sfr DIR5 = 0xF8; /* in mapped SFR area */
44 =2 sfr P6 = 0xDB;
45 =2 sfr P7 = 0xFA;
46 =2
C51 COMPILER V6.10 SCC_M515 04/19/2001 14:10:31 PAGE 3
47 =2 /* Serial Channel */
48 =2 sfr SCON = 0x98;
49 =2 sfr SBUF = 0x99;
50 =2 sfr SRELL = 0xAA;
51 =2 sfr SRELH = 0xBA;
52 =2
53 =2 /* SSC Interface */
54 =2 sfr SSCCON = 0x93;
55 =2 sfr STB = 0x94;
56 =2 sfr SRB = 0x95;
57 =2 sfr SCF = 0xAB;
58 =2 sfr SCIEN = 0xAC;
59 =2 sfr SSCMOD = 0x96;
60 =2
61 =2 /* Timer0 / Timer1 */
62 =2 sfr TCON = 0x88;
63 =2 sfr TMOD = 0x89;
64 =2 sfr TL0 = 0x8A;
65 =2 sfr TL1 = 0x8B;
66 =2 sfr TH0 = 0x8C;
67 =2 sfr TH1 = 0x8D;
68 =2
69 =2 /* CAP/COM Unit / Timer2 */
70 =2 sfr CCEN = 0xC1;
71 =2 sfr CCL1 = 0xC2;
72 =2 sfr CCH1 = 0xC3;
73 =2 sfr CCL2 = 0xC4;
74 =2 sfr CCH2 = 0xC5;
75 =2 sfr CCL3 = 0xC6;
76 =2 sfr CCH3 = 0xC7;
77 =2 sfr T2CON = 0xC8;
78 =2 sfr CRCL = 0xCA;
79 =2 sfr CRCH = 0xCB;
80 =2 sfr TL2 = 0xCC;
81 =2 sfr TH2 = 0xCD;
82 =2
83 =2 /* Watchdog */
84 =2 sfr WDTREL = 0x86;
85 =2
86 =2 /* Power Save Moders */
87 =2 sfr PCON = 0x87;
88 =2 sfr PCON1 = 0x88; /* in mapped SFR area */
89 =2
90 =2
91 =2 /* BIT Register */
92 =2 /* PSW */
93 =2 sbit CY = PSW^7;
94 =2 sbit AC = PSW^6;
95 =2 sbit F0 = PSW^5;
96 =2 sbit RS1 = PSW^4;
97 =2 sbit RS0 = PSW^3;
98 =2 sbit OV = PSW^2;
99 =2 sbit F1 = PSW^1;
100 =2 sbit P = PSW^0;
101 =2
102 =2 /* TCON */
103 =2 sbit TF1 = TCON^7;
104 =2 sbit TR1 = TCON^6;
105 =2 sbit TF0 = TCON^5;
106 =2 sbit TR0 = TCON^4;
107 =2 sbit IE1 = TCON^3;
108 =2 sbit IT1 = TCON^2;
C51 COMPILER V6.10 SCC_M515 04/19/2001 14:10:31 PAGE 4
109 =2 sbit IE0 = TCON^1;
110 =2 sbit IT0 = TCON^0;
111 =2
112 =2 /* IEN0 */
113 =2 sbit EAL = IEN0^7;
114 =2 sbit WDT = IEN0^6;
115 =2 sbit ET2 = IEN0^5;
116 =2 sbit ES = IEN0^4;
117 =2 sbit ET1 = IEN0^3;
118 =2 sbit EX1 = IEN0^2;
119 =2 sbit ET0 = IEN0^1;
120 =2 sbit EX0 = IEN0^0;
121 =2
122 =2 /* IEN1 */
123 =2 sbit EXEN2 = IEN1^7;
124 =2 sbit SWDT = IEN1^6;
125 =2 sbit EX6 = IEN1^5;
126 =2 sbit EX5 = IEN1^4;
127 =2 sbit EX4 = IEN1^3;
128 =2 sbit EX3 = IEN1^2;
129 =2 sbit EX2 = IEN1^1;
130 =2 sbit EADC = IEN1^0;
131 =2
132 =2 /* P3 */
133 =2 sbit RD = P3^7;
134 =2 sbit WR = P3^6;
135 =2 sbit T1 = P3^5;
136 =2 sbit T0 = P3^4;
137 =2 sbit INT1 = P3^3;
138 =2 sbit INT0 = P3^2;
139 =2 sbit TXD = P3^1;
140 =2 sbit RXD = P3^0;
141 =2
142 =2 /* SCON */
143 =2 sbit SM0 = SCON^7;
144 =2 sbit SM1 = SCON^6;
145 =2 sbit SM2 = SCON^5;
146 =2 sbit REN = SCON^4;
147 =2 sbit TB8 = SCON^3;
148 =2 sbit RB8 = SCON^2;
149 =2 sbit TI = SCON^1;
150 =2 sbit RI = SCON^0;
151 =2
152 =2 /* T2CON */
153 =2 sbit T2PS = T2CON^7;
154 =2 sbit I3FR = T2CON^6;
155 =2 sbit I2FR = T2CON^5;
156 =2 sbit T2R1 = T2CON^4;
157 =2 sbit T2R0 = T2CON^3;
158 =2 sbit T2CM = T2CON^2;
159 =2 sbit T2I1 = T2CON^1;
160 =2 sbit T2I0 = T2CON^0;
161 =2
162 =2 /* ADCON0 */
163 =2 sbit BD = ADCON0^7;
164 =2 sbit CLK = ADCON0^6;
165 =2 sbit ADEX = ADCON0^5;
166 =2 sbit BSY = ADCON0^4;
167 =2 sbit ADM = ADCON0^3;
168 =2 sbit MX2 = ADCON0^2;
169 =2 sbit MX1 = ADCON0^1;
170 =2 sbit MX0 = ADCON0^0;
C51 COMPILER V6.10 SCC_M515 04/19/2001 14:10:31 PAGE 5
171 =2
172 =2 /* IRCON */
173 =2 sbit EXF2 = IRCON^7;
174 =2 sbit TF2 = IRCON^6;
175 =2 sbit IEX6 = IRCON^5;
176 =2 sbit IEX5 = IRCON^4;
177 =2 sbit IEX4 = IRCON^3;
178 =2 sbit IEX3 = IRCON^2;
179 =2 sbit IEX2 = IRCON^1;
180 =2 sbit IADC = IRCON^0;
181 =2
182 =2 /* P1 */
183 =2 sbit T2 = P1^7;
184 =2 sbit CLKOUT = P1^6;
185 =2 sbit T2EX = P1^5;
186 =2 sbit INT2 = P1^4;
187 =2 sbit INT6 = P1^3;
188 =2 sbit INT5 = P1^2;
189 =2 sbit INT4 = P1^1;
190 =2 sbit INT3 = P1^0;
191 =2
192 =2 /* P4 */
193 =2 sbit RXDC = P4^7;
194 =2 sbit TXDC = P4^6;
195 =2 sbit INT8 = P4^5;
196 =2 sbit SLS = P4^4;
197 =2 sbit STO = P4^3;
198 =2 sbit SRI = P4^2;
199 =2 sbit SCLK = P4^1;
200 =2 sbit ADST = P4^0;
33 =1
34 =1 // Include oscillator / chip details here
35 =1 // (essential if generic delays / timeouts are used)
36 =1 // -
37 =1 // Oscillator / resonator frequency (in Hz) e.g. (11059200UL)
38 =1 #define OSC_FREQ (10000000UL)
39 =1
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