📄 msp430x14x_ext.h.bak
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#define SHT0_10 10*0x100
#define SHT0_11 11*0x100
#define SHT0_12 12*0x100
#define SHT0_13 13*0x100
#define SHT0_14 14*0x100
#define SHT0_15 15*0x100
#define SHT1_0 00*0x1000
#define SHT1_1 01*0x1000
#define SHT1_2 02*0x1000
#define SHT1_3 03*0x1000
#define SHT1_4 04*0x1000
#define SHT1_5 05*0x1000
#define SHT1_6 06*0x1000
#define SHT1_7 07*0x1000
#define SHT1_8 08*0x1000
#define SHT1_9 09*0x1000
#define SHT1_10 10*0x1000
#define SHT1_11 11*0x1000
#define SHT1_12 12*0x1000
#define SHT1_13 13*0x1000
#define SHT1_14 14*0x1000
#define SHT1_15 15*0x1000
#define ADC12BUSY 0x0001 /* ADC12CTL1 */
#define CONSEQ_0 00*2
#define CONSEQ_1 01*2
#define CONSEQ_2 02*2
#define CONSEQ_3 03*2
#define ADC12SSEL_0 00*8
#define ADC12SSEL_1 01*8
#define ADC12SSEL_2 02*8
#define ADC12SSEL_3 03*8
#define ADC12DIV_0 00*0x20
#define ADC12DIV_1 01*0x20
#define ADC12DIV_2 02*0x20
#define ADC12DIV_3 03*0x20
#define ADC12DIV_4 04*0x20
#define ADC12DIV_5 05*0x20
#define ADC12DIV_6 06*0x20
#define ADC12DIV_7 07*0x20
#define ISSH 0x0100
#define SHP 0x0200
#define SHS_0 00*0x400
#define SHS_1 01*0x400
#define SHS_2 02*0x400
#define SHS_3 03*0x400
#define CSTARTADD_0 00*0x1000
#define CSTARTADD_1 01*0x1000
#define CSTARTADD_2 02*0x1000
#define CSTARTADD_3 03*0x1000
#define CSTARTADD_4 04*0x1000
#define CSTARTADD_5 05*0x1000
#define CSTARTADD_6 06*0x1000
#define CSTARTADD_7 07*0x1000
#define CSTARTADD_8 08*0x1000
#define CSTARTADD_9 09*0x1000
#define CSTARTADD_10 10*0x1000
#define CSTARTADD_11 11*0x1000
#define CSTARTADD_12 12*0x1000
#define CSTARTADD_13 13*0x1000
#define CSTARTADD_14 14*0x1000
#define CSTARTADD_15 15*0x1000
#define INCH_0 00 /* ADC12CTLx */
#define INCH_1 01
#define INCH_2 02
#define INCH_3 03
#define INCH_4 04
#define INCH_5 05
#define INCH_6 06
#define INCH_7 07
#define INCH_8 08
#define INCH_9 09
#define INCH_10 10
#define INCH_11 11
#define INCH_12 12
#define INCH_13 13
#define INCH_14 14
#define INCH_15 15
#define SREF_0 00*0x10
#define SREF_1 01*0x10
#define SREF_2 02*0x10
#define SREF_3 03*0x10
#define SREF_4 04*0x10
#define SREF_5 05*0x10
#define SREF_6 06*0x10
#define SREF_7 07*0x10
#define EOS 0x80
/************************************************************
* Interrupt Vectors (offset from 0xFFE0)
************************************************************/
#define PORT2_VECTOR 1 * 2 /* 0xFFE2 Port 2 */
#define UART1TX_VECTOR 2 * 2 /* 0xFFE4 UART 1 Transmit */
#define UART1RX_VECTOR 3 * 2 /* 0xFFE6 UART 1 Receive */
#define PORT1_VECTOR 4 * 2 /* 0xFFE8 Port 1 */
#define TIMERA1_VECTOR 5 * 2 /* 0xFFEA Timer A CC1-2, TA */
#define TIMERA0_VECTOR 6 * 2 /* 0xFFEC Timer A CC0 */
#define ADC_VECTOR 7 * 2 /* 0xFFEE ADC */
#define UART0TX_VECTOR 8 * 2 /* 0xFFF0 UART 0 Transmit */
#define UART0RX_VECTOR 9 * 2 /* 0xFFF2 UART 0 Receive */
#define WDT_VECTOR 10 * 2 /* 0xFFF4 Watchdog Timer */
#define COMPARATORA_VECTOR 11 * 2 /* 0xFFF6 Comparator A */
#define TIMERB1_VECTOR 12 * 2 /* 0xFFF8 Timer B 1-7 */
#define TIMERB0_VECTOR 13 * 2 /* 0xFFFA Timer B 0 */
#define NMI_VECTOR 14 * 2 /* 0xFFFC Non-maskable */
#define RESET_VECTOR 15 * 2 /* 0xFFFE Reset [Highest Priority] */
/************************************************************
* End of Modules
************************************************************/
/************************************************************
* MACRO definition By Hujinchun
************************************************************/
#include "gtcfg.h"
#define UBR_115200 (UARTCLK_USER/115200)
#define UBR_57600 (UARTCLK_USER/57600)
#define UBR_38400 (UARTCLK_USER/38400)
#define UBR_19200 (UARTCLK_USER/19200)
#define UBR_9600 (UARTCLK_USER/9600)
#define UBR_4800 (UARTCLK_USER/4800)
#define UBR_2400 (UARTCLK_USER/2400)
#define UBR_1200 (UARTCLK_USER/1200)
#define UMCTL_115200 (UARTCLK_USER * 8 - UBR_115200 * 8 * 115200)/115200
#define UMCTL_57600 (UARTCLK_USER * 8 - UBR_57600 * 8 * 57600)/57600
#define UMCTL_38400 (UARTCLK_USER * 8 - UBR_38400 * 8 * 38400)/38400
#define UMCTL_19200 (UARTCLK_USER * 8 - UBR_19200 * 8 * 19200)/19200
#define UMCTL_9600 (UARTCLK_USER * 8 - UBR_9600 * 8 * 9600)/9600
#define UMCTL_4800 (UARTCLK_USER * 8 - UBR_4800 * 8 * 4800)/4800
#define UMCTL_2400 (UARTCLK_USER * 8 - UBR_2400 * 8 * 2400)/2400
#define UMCTL_1200 (UARTCLK_USER * 8 - UBR_1200 * 8 * 1200)/1200
#define DCOCTL_DCO_FRQ0 0X00
#define DCOCTL_DCO_FRQ1 0X20
#define DCOCTL_DCO_FRQ2 0X40
#define DCOCTL_DCO_FRQ3 0X60
#define DCOCTL_DCO_FRQ4 0X80
#define DCOCTL_DCO_FRQ5 0XA0
#define DCOCTL_DCO_FRQ6 0XC0
#define DCOCTL_DCO_FRQ7 0XE0
#define BCSCTRL1_XT2ON 0X00
#define BCSCTRL1_XT2OFF 0X80
#define BCSCTRL1_LFXT1_LFMODE 0X00
#define BCSCTRL1_LFXT1_HFMODE 0X40
#define BCSCTRL1_ACLK_DIVBY1 0X00
#define BCSCTRL1_ACLK_DIVBY2 0X10
#define BCSCTRL1_ACLK_DIVBY4 0X20
#define BCSCTRL1_ACLK_DIVBY8 0X30
#define BCSCTRL1_ACLK_FEQ0 0X00
#define BCSCTRL1_ACLK_FEQ1 0X01
#define BCSCTRL1_ACLK_FEQ2 0X02
#define BCSCTRL1_ACLK_FEQ3 0X03
#define BCSCTRL1_ACLK_FEQ4 0X04
#define BCSCTRL1_ACLK_FEQ5 0X05
#define BCSCTRL1_ACLK_FEQ6 0X06
#define BCSCTRL1_ACLK_FEQ7 0X07
#define BCSCTRL2_MCLK_DCOCLK 0X00
#define BCSCTRL2_MCLK_TX2CLK 0X80
#define BCSCTRL2_MCLK_TX1CLK 0XC0
#define BCSCTRL2_MCLK_DIVBY1 0X00
#define BCSCTRL2_MCLK_DIVBY2 0X10
#define BCSCTRL2_MCLK_DIVBY4 0X20
#define BCSCTRL2_MCLK_DIVBY8 0X30
#define BCSCTRL2_SMCLK_DCOCLK 0X00
#define BCSCTRL2_SMCLK_TX2CLK 0X08
#define BCSCTRL2_SMCLK_DIVBY1 0X00
#define BCSCTRL2_SMCLK_DIVBY2 0X20
#define BCSCTRL2_SMCLK_DIVBY4 0X40
#define BCSCTRL2_SMCLK_DIVBY8 0X60
#define BCSCTRL2_DCOR_INNER 0X00
#define BCSCTRL2_DCOR_EXT 0X01
#define U0CLT_EN_PE 0X80
#define U0CLT_DIS_PE 0X00
#define U0CLT_PEBIT_ODD 0X00
#define U0CLT_PEBIT_EVEN 0X40
#define U0CLT_SBITS_1BIT 0X00
#define U0CLT_SBITS_2BITS 0X20
#define U0CLT_CHARBITS_7BITS 0X00
#define U0CLT_CHARBITS_8BITS 0X10
#define U0CLT_EN_LISTEN 0X08
#define U0CLT_DIS_LISTEN 0X00
#define U0CLT_SYNC_MODE 0X04
#define U0CLT_ASYNC_MODE 0X00
#define U0CLT_MUTLI_MODE 0X02
#define U0CLT_P2P_MODE 0X00
#define U0CLT_SWRST_SETMODE 0X01
#define U0CLT_SWRST_NORMAL 0X00
///////////////////////////////////////////////////////////
#define U1CLT_EN_PE 0X80
#define U1CLT_DIS_PE 0X00
#define U1CLT_PEBIT_ODD 0X00
#define U1CLT_PEBIT_EVEN 0X40
#define U1CLT_SBITS_1BIT 0X00
#define U1CLT_SBITS_2BITS 0X20
#define U1CLT_CHARBITS_7BITS 0X00
#define U1CLT_CHARBITS_8BITS 0X10
#define U1CLT_EN_LISTEN 0X08
#define U1CLT_DIS_LISTEN 0X00
#define U1CLT_SYNC_MODE 0X04
#define U1CLT_ASYNC_MODE 0X00
#define U1CLT_MUTLI_MODE 0X02
#define U1CLT_P2P_MODE 0X00
#define U1CLT_SWRST_SETMODE 0X01
#define U1CLT_SWRST_NORMAL 0X00
////////////////////////////////////////////////////////////
#define U0TCTL_SPI_NORMALCLK 0X00
#define U0TCTL_SPI_DELAYHALFCLK 0X80
#define U0TCTL_CLKPL_POS 0X00
#define U0TCTL_CLKPL_NEG 0X40
#define U0TCTL_CLKSEL_ACLK 0X10
#define U0TCTL_CLKSEL_SMCLK 0X20
#define U0TCTL_RXEDGE_STATUS 0X08
#define U0TCTL_TXEPT_STATUS 0X01
///////////////////////////////////////////////////////////
#define URCTL_FE_STATUS 0X80
#define URCTL_PE_STATUS 0X40
#define URCTL_OE_STATUS 0X20
#define URCTL_BRK_STATUS 0X10
#define URCTL_EN_RXERRINT 0X08
#define URCTL_DIS_RXERRINT 0X00
#define URCTL_EN_RXWAKEINT 0X04
#define URCTL_DIS_RXWAKEINT 0X00
#define URCTL_RXERR_STATUS 0X01
///////////////////////////////////////////////////////////
#define TACTLA_CLKSEL_EXPIN 0X0000
#define TACTLA_CLKSEL_ACLK 0X0100
#define TACTLA_CLKSEL_SMCLK 0X0200
#define TACTLA_CLKSEL_INCLK 0X0300
#define TACTLA_DIVBY1 0X00
#define TACTLA_DIVBY2 0X40
#define TACTLA_DIVBY4 0X80
#define TACTLA_DIVBY8 0XC0
#define TACTLA_MODESEL_PAUSE 0X00
#define TACTLA_MODESEL_INC2CCR0 0X10
#define TACTLA_MODESEL_INC 0X20
#define TACTLA_MODESEL_INCDECBYCCR0 0X30
#define TACTLA_CLRCNTR 0X04
#define TACTLA_ENINT 0X02
#define TACTLA_OVFLAG 0X01
#endif /* #ifndef __msp430F14x */
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