📄 msp430x14x_ext.h.bak
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#define TBSSEL_3 03*0x0100 /* Clock Source: INCLK */
#define CNTL_0 00*0x0800 /* Counter lenght: 16 bit */
#define CNTL_1 01*0x0800 /* Counter lenght: 12 bit */
#define CNTL_2 02*0x0800 /* Counter lenght: 10 bit */
#define CNTL_3 03*0x0800 /* Counter lenght: 8 bit */
#define SHR_0 00*0x2000 /* Timer B Group: 0 - individually */
#define SHR_1 01*0x2000 /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
#define SHR_2 02*0x2000 /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
#define SHR_3 03*0x2000 /* Timer B Group: 3 - 1 group (all) */
#define TBCLGRP_0 00*0x2000 /* Timer B Group: 0 - individually */
#define TBCLGRP_1 01*0x2000 /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
#define TBCLGRP_2 02*0x2000 /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
#define TBCLGRP_3 03*0x2000 /* Timer B Group: 3 - 1 group (all) */
/* Additional Timer B Control Register bits are defined in Timer A */
#define SLSHR1 0x0400 /* Compare latch load source 1 */
#define SLSHR0 0x0200 /* Compare latch load source 0 */
#define CLLD1 0x0400 /* Compare latch load source 1 */
#define CLLD0 0x0200 /* Compare latch load source 0 */
#define SLSHR_0 00*0x0200 /* Compare latch load sourec : 0 - immediate */
#define SLSHR_1 01*0x0200 /* Compare latch load sourec : 1 - TBR counts to 0 */
#define SLSHR_2 02*0x0200 /* Compare latch load sourec : 2 - up/down */
#define SLSHR_3 03*0x0200 /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
#define CLLD_0 00*0x0200 /* Compare latch load sourec : 0 - immediate */
#define CLLD_1 01*0x0200 /* Compare latch load sourec : 1 - TBR counts to 0 */
#define CLLD_2 02*0x0200 /* Compare latch load sourec : 2 - up/down */
#define CLLD_3 03*0x0200 /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
/************************************************************
* Basic Clock Module
************************************************************/
#define DCOCTL_ 0x0056 /* DCO Clock Frequency Control */
sfrb DCOCTL = DCOCTL_;
#define BCSCTL1_ 0x0057 /* Basic Clock System Control 1 */
sfrb BCSCTL1 = BCSCTL1_;
#define BCSCTL2_ 0x0058 /* Basic Clock System Control 2 */
sfrb BCSCTL2 = BCSCTL2_;
#define MOD0 0x01 /* Modulation Bit 0 */
#define MOD1 0x02 /* Modulation Bit 1 */
#define MOD2 0x04 /* Modulation Bit 2 */
#define MOD3 0x08 /* Modulation Bit 3 */
#define MOD4 0x10 /* Modulation Bit 4 */
#define DCO0 0x20 /* DCO Select Bit 0 */
#define DCO1 0x40 /* DCO Select Bit 1 */
#define DCO2 0x80 /* DCO Select Bit 2 */
#define RSEL0 0x01 /* Resistor Select Bit 0 */
#define RSEL1 0x02 /* Resistor Select Bit 1 */
#define RSEL2 0x04 /* Resistor Select Bit 2 */
#define XT5V 0x08 /* XT5V should always be reset */
#define DIVA0 0x10 /* ACLK Divider 0 */
#define DIVA1 0x20 /* ACLK Divider 1 */
#define XTS 0x40 /* LFXTCLK 0:Low Freq. / 1: High Freq. */
#define XT2OFF 0x80 /* Enable XT2CLK */
#define DIVA_0 0x00 /* ACLK Divider 0: /1 */
#define DIVA_1 0x10 /* ACLK Divider 1: /2 */
#define DIVA_2 0x20 /* ACLK Divider 2: /4 */
#define DIVA_3 0x30 /* ACLK Divider 3: /8 */
#define DCOR 0x01 /* Enable External Resistor : 1 */
#define DIVS0 0x02 /* SMCLK Divider 0 */
#define DIVS1 0x04 /* SMCLK Divider 1 */
#define SELS 0x08 /* MCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
#define DIVM0 0x10 /* MCLK Divider 0 */
#define DIVM1 0x20 /* MCLK Divider 1 */
#define SELM0 0x40 /* SMCLK Source Select 0 */
#define SELM1 0x80 /* SMCLK Source Select 1 */
#define DIVS_0 0x00 /* SMCLK Divider 0: /1 */
#define DIVS_1 0x02 /* SMCLK Divider 1: /2 */
#define DIVS_2 0x04 /* SMCLK Divider 2: /4 */
#define DIVS_3 0x06 /* SMCLK Divider 3: /8 */
#define DIVM_0 0x00 /* MCLK Divider 0: /1 */
#define DIVM_1 0x10 /* MCLK Divider 1: /2 */
#define DIVM_2 0x20 /* MCLK Divider 2: /4 */
#define DIVM_3 0x30 /* MCLK Divider 3: /8 */
#define SELM_0 0x00 /* SMCLK Source Select 0: DCOCLK */
#define SELM_1 0x40 /* SMCLK Source Select 1: DCOCLK */
#define SELM_2 0x80 /* SMCLK Source Select 2: XT2CLK/LFXTCLK */
#define SELM_3 0xC0 /* SMCLK Source Select 3: LFXTCLK */
/*************************************************************
* Flash Memory
*************************************************************/
#define FCTL1_ 0x0128 /* FLASH Control 1 */
sfrw FCTL1 = FCTL1_;
#define FCTL2_ 0x012A /* FLASH Control 2 */
sfrw FCTL2 = FCTL2_;
#define FCTL3_ 0x012C /* FLASH Control 3 */
sfrw FCTL3 = FCTL3_;
#define FRKEY 0x9600 /* Flash key returned by read */
#define FWKEY 0xA500 /* Flash key for write */
#define FXKEY 0x3300 /* for use with XOR instruction */
#define ERASE 0x0002 /* Enable bit for Flash segment erase */
#define MERAS 0x0004 /* Enable bit for Flash mass erase */
#define WRT 0x0040 /* Enable bit for Flash write */
#define BLKWRT 0x0080 /* Enable bit for Flash segment write */
#define SEGWRT 0x0080 /* old definition */ /* Enable bit for Flash segment write */
#define FN0 0x0001 /* Devide Flash clock by: 2^0 */
#define FN1 0x0002 /* Devide Flash clock by: 2^1 */
#define FN2 0x0004 /* Devide Flash clock by: 2^2 */
#define FN3 0x0008 /* Devide Flash clock by: 2^3 */
#define FN4 0x0010 /* Devide Flash clock by: 2^4 */
#define FN5 0x0020 /* Devide Flash clock by: 2^5 */
#define FSSEL0 0x0040 /* Flash clock select 0 */ /* to distinguish from UART SSELx */
#define FSSEL1 0x0080 /* Flash clock select 1 */
#define FSSEL_0 0x0000 /* Flash clock select: 0 - ACLK */
#define FSSEL_1 0x0040 /* Flash clock select: 1 - MCLK */
#define FSSEL_2 0x0080 /* Flash clock select: 2 - SMCLK */
#define FSSEL_3 0x00C0 /* Flash clock select: 3 - SMCLK */
#define BUSY 0x0001 /* Flash busy: 1 */
#define KEYV 0x0002 /* Flash Key violation flag */
#define ACCVIFG 0x0004 /* Flash Access violation flag */
#define WAIT 0x0008 /* Wait flag for segment write */
#define LOCK 0x0010 /* Lock bit: 1 - Flash is locked (read only) */
#define EMEX 0x0020 /* Flash Emergency Exit */
/************************************************************
* Comparator A
************************************************************/
#define CACTL1_ 0x0059 /* Comparator A Control 1 */
sfrb CACTL1 = CACTL1_;
#define CACTL2_ 0x005A /* Comparator A Control 2 */
sfrb CACTL2 = CACTL2_;
#define CAPD_ 0x005B /* Comparator A Port Disable */
sfrb CAPD = CAPD_;
#define CAIFG 0x01 /* Comp. A Interrupt Flag */
#define CAIE 0x02 /* Comp. A Interrupt Enable */
#define CAIES 0x04 /* Comp. A Int. Edge Select: 0:rising / 1:falling */
#define CAON 0x08 /* Comp. A enable */
#define CAREF0 0x10 /* Comp. A Internal Reference Select 0 */
#define CAREF1 0x20 /* Comp. A Internal Reference Select 1 */
#define CARSEL 0x40 /* Comp. A Internal Reference Enable */
#define CAEX 0x80 /* Comp. A Exchange Inputs */
#define CAREF_0 0x00 /* Comp. A Int. Ref. Select 0 : Off */
#define CAREF_1 0x10 /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
#define CAREF_2 0x20 /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
#define CAREF_3 0x30 /* Comp. A Int. Ref. Select 3 : Vt*/
#define CAOUT 0x01 /* Comp. A Output */
#define CAF 0x02 /* Comp. A Enable Output Filter */
#define P2CA0 0x04 /* Comp. A Connect External Signal to CA0 : 1 */
#define P2CA1 0x08 /* Comp. A Connect External Signal to CA1 : 1 */
#define CACTL24 0x10
#define CACTL25 0x20
#define CACTL26 0x40
#define CACTL27 0x80
#define CAPD0 0x01 /* Comp. A Disable Input Buffer of Port Register .0 */
#define CAPD1 0x02 /* Comp. A Disable Input Buffer of Port Register .1 */
#define CAPD2 0x04 /* Comp. A Disable Input Buffer of Port Register .2 */
#define CAPD3 0x08 /* Comp. A Disable Input Buffer of Port Register .3 */
#define CAPD4 0x10 /* Comp. A Disable Input Buffer of Port Register .4 */
#define CAPD5 0x20 /* Comp. A Disable Input Buffer of Port Register .5 */
#define CAPD6 0x40 /* Comp. A Disable Input Buffer of Port Register .6 */
#define CAPD7 0x80 /* Comp. A Disable Input Buffer of Port Register .7 */
/************************************************************
* ADC12
************************************************************/
#define ADC12CTL0_ 0x01A0 /* ADC12 Control 0 */
sfrw ADC12CTL0 = ADC12CTL0_;
#define ADC12CTL1_ 0x01A2 /* ADC12 Control 1 */
sfrw ADC12CTL1 = ADC12CTL1_;
#define ADC12IFG_ 0x01A4 /* ADC12 Interrupt Flag */
sfrw ADC12IFG = ADC12IFG_;
#define ADC12IE_ 0x01A6 /* ADC12 Interrupt Enable */
sfrw ADC12IE = ADC12IE_;
#define ADC12IV_ 0x01A8 /* ADC12 Interrupt Vector Word */
sfrw ADC12IV = ADC12IV_;
#define ADC12MEM_ 0x0140 /* ADC12 Conversion Memory */
#ifndef __IAR_SYSTEMS_ICC
#define ADC12MEM ADC12MEM_ /* ADC12 Conversion Memory (for assembler) */
#else
#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */
#endif
#define ADC12MEM0_ ADC12MEM_ /* ADC12 Conversion Memory 0 */
sfrw ADC12MEM0 = ADC12MEM0_;
#define ADC12MEM1_ 0x0142 /* ADC12 Conversion Memory 1 */
sfrw ADC12MEM1 = ADC12MEM1_;
#define ADC12MEM2_ 0x0144 /* ADC12 Conversion Memory 2 */
sfrw ADC12MEM2 = ADC12MEM2_;
#define ADC12MEM3_ 0x0146 /* ADC12 Conversion Memory 3 */
sfrw ADC12MEM3 = ADC12MEM3_;
#define ADC12MEM4_ 0x0148 /* ADC12 Conversion Memory 4 */
sfrw ADC12MEM4 = ADC12MEM4_;
#define ADC12MEM5_ 0x014A /* ADC12 Conversion Memory 5 */
sfrw ADC12MEM5 = ADC12MEM5_;
#define ADC12MEM6_ 0x014C /* ADC12 Conversion Memory 6 */
sfrw ADC12MEM6 = ADC12MEM6_;
#define ADC12MEM7_ 0x014E /* ADC12 Conversion Memory 7 */
sfrw ADC12MEM7 = ADC12MEM7_;
#define ADC12MEM8_ 0x0150 /* ADC12 Conversion Memory 8 */
sfrw ADC12MEM8 = ADC12MEM8_;
#define ADC12MEM9_ 0x0152 /* ADC12 Conversion Memory 9 */
sfrw ADC12MEM9 = ADC12MEM9_;
#define ADC12MEM10_ 0x0154 /* ADC12 Conversion Memory 10 */
sfrw ADC12MEM10 = ADC12MEM10_;
#define ADC12MEM11_ 0x0156 /* ADC12 Conversion Memory 11 */
sfrw ADC12MEM11 = ADC12MEM11_;
#define ADC12MEM12_ 0x0158 /* ADC12 Conversion Memory 12 */
sfrw ADC12MEM12 = ADC12MEM12_;
#define ADC12MEM13_ 0x015A /* ADC12 Conversion Memory 13 */
sfrw ADC12MEM13 = ADC12MEM13_;
#define ADC12MEM14_ 0x015C /* ADC12 Conversion Memory 14 */
sfrw ADC12MEM14 = ADC12MEM14_;
#define ADC12MEM15_ 0x015E /* ADC12 Conversion Memory 15 */
sfrw ADC12MEM15 = ADC12MEM15_;
#define ADC12MCTL_ 0x0080 /* ADC12 Memory Control */
#ifndef __IAR_SYSTEMS_ICC
#define ADC12MCTL ADC12MCTL_ /* ADC12 Memory Control (for assembler) */
#else
#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */
#endif
#define ADC12MCTL0_ ADC12MCTL_ /* ADC12 Memory Control 0 */
sfrb ADC12MCTL0 = ADC12MCTL0_;
#define ADC12MCTL1_ 0x0081 /* ADC12 Memory Control 1 */
sfrb ADC12MCTL1 = ADC12MCTL1_;
#define ADC12MCTL2_ 0x0082 /* ADC12 Memory Control 2 */
sfrb ADC12MCTL2 = ADC12MCTL2_;
#define ADC12MCTL3_ 0x0083 /* ADC12 Memory Control 3 */
sfrb ADC12MCTL3 = ADC12MCTL3_;
#define ADC12MCTL4_ 0x0084 /* ADC12 Memory Control 4 */
sfrb ADC12MCTL4 = ADC12MCTL4_;
#define ADC12MCTL5_ 0x0085 /* ADC12 Memory Control 5 */
sfrb ADC12MCTL5 = ADC12MCTL5_;
#define ADC12MCTL6_ 0x0086 /* ADC12 Memory Control 6 */
sfrb ADC12MCTL6 = ADC12MCTL6_;
#define ADC12MCTL7_ 0x0087 /* ADC12 Memory Control 7 */
sfrb ADC12MCTL7 = ADC12MCTL7_;
#define ADC12MCTL8_ 0x0088 /* ADC12 Memory Control 8 */
sfrb ADC12MCTL8 = ADC12MCTL8_;
#define ADC12MCTL9_ 0x0089 /* ADC12 Memory Control 9 */
sfrb ADC12MCTL9 = ADC12MCTL9_;
#define ADC12MCTL10_ 0x008A /* ADC12 Memory Control 10 */
sfrb ADC12MCTL10 = ADC12MCTL10_;
#define ADC12MCTL11_ 0x008B /* ADC12 Memory Control 11 */
sfrb ADC12MCTL11 = ADC12MCTL11_;
#define ADC12MCTL12_ 0x008C /* ADC12 Memory Control 12 */
sfrb ADC12MCTL12 = ADC12MCTL12_;
#define ADC12MCTL13_ 0x008D /* ADC12 Memory Control 13 */
sfrb ADC12MCTL13 = ADC12MCTL13_;
#define ADC12MCTL14_ 0x008E /* ADC12 Memory Control 14 */
sfrb ADC12MCTL14 = ADC12MCTL14_;
#define ADC12MCTL15_ 0x008F /* ADC12 Memory Control 15 */
sfrb ADC12MCTL15 = ADC12MCTL15_;
#define ADC12SC 0x001 /* ADC12CTL0 */
#define ENC 0x002
#define ADC12TOVIE 0x004
#define ADC12OVIE 0x008
#define ADC12ON 0x010
#define REFON 0x020
#define REF2_5V 0x040
#define MSH 0x080
#define MSC 0x080
#define SHT0_0 00*0x100
#define SHT0_1 01*0x100
#define SHT0_2 02*0x100
#define SHT0_3 03*0x100
#define SHT0_4 04*0x100
#define SHT0_5 05*0x100
#define SHT0_6 06*0x100
#define SHT0_7 07*0x100
#define SHT0_8 08*0x100
#define SHT0_9 09*0x100
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