gt2510.h

MCP2510的CAN控制器程序

#define MCPREG_RXF0SIDH      0X00//FILTER 0 STANDARD IDENTIFIER HIGH
#define MCPREG_RXF1SIDH      0X04//FILTER 1 STANDARD IDENTIFIER HIGH
#define MCPREG_RXF2SIDH      0X08//FILTER 2 STANDARD IDENTIFIER HIGH
#define MCPREG_RXF3SIDH      0X10//FILTER 3 STANDARD IDENTIFIER HIGH
#define MCPREG_RXF4SIDH      0X14//FILTER 4 STANDARD IDENTIFIER HIGH
#define MCPREG_RXF5SIDH      0X18//FILTER 5 STANDARD IDENTIFIER HIGH

#define MCPREG_RXF0SIDL      0x01//FILTER 0 STANDARD IDENTIFIER LOW
#define MCPREG_RXF1SIDL      0x05//FILTER 1 STANDARD IDENTIFIER LOW
#define MCPREG_RXF2SIDL      0x06//FILTER 2 STANDARD IDENTIFIER LOW
#define MCPREG_RXF3SIDL      0x11//FILTER 3 STANDARD IDENTIFIER LOW
#define MCPREG_RXF4SIDL      0x15//FILTER 4 STANDARD IDENTIFIER LOW
#define MCPREG_RXF5SIDL      0x19//FILTER 5 STANDARD IDENTIFIER LOW

#define RXFSIDLBIT_EXIDE     0X08//Extended Identifier Enable
                                 //1 = Filter is applied only to Extended Frames
                                 //0 = Filter is applied only to Standard Frames
//bit 7-5 = SID<2:0>: Standard Identifier Filter Bits <2:0>
//These bits hold the filter bits to be applied to bits <2:0> of the Standard Identifier portion of a
//received message

//bit 1-0 = EID<17:16>: Exended Identifier Filter Bits <17:16>
//These bits hold the filter bits to be applied to bits <17:16> of the Extended Identifier portion of
//a received message

#define MCPREG_RXF0EID8      0x02//FILTER 0 EXTENDED IDENTIFIER HIGH
#define MCPREG_RXF1EID8      0x06//FILTER 1 EXTENDED IDENTIFIER HIGH
#define MCPREG_RXF2EID8      0x0A//FILTER 2 EXTENDED IDENTIFIER HIGH
#define MCPREG_RXF3EID8      0x12//FILTER 3 EXTENDED IDENTIFIER HIGH
#define MCPREG_RXF4EID8      0x16//FILTER 4 EXTENDED IDENTIFIER HIGH
#define MCPREG_RXF5EID8      0x1A//FILTER 5 EXTENDED IDENTIFIER HIGH

//EID<15:8>: Extended Identifier Bits <15:8>
//These bits hold the filter bits to be applied to bits <15:8> of the Extended Identifier portion of a
//received message

#define MCPREG_RXF0EID0      0X03//FILTER 0 EXTENDED IDENTIFIER LOW
#define MCPREG_RXF1EID0      0X07//FILTER 1 EXTENDED IDENTIFIER LOW
#define MCPREG_RXF2EID0      0X0B//FILTER 2 EXTENDED IDENTIFIER LOW
#define MCPREG_RXF3EID0      0X13//FILTER 3 EXTENDED IDENTIFIER LOW
#define MCPREG_RXF4EID0      0X17//FILTER 4 EXTENDED IDENTIFIER LOW
#define MCPREG_RXF5EID0      0X1B//FILTER 5 EXTENDED IDENTIFIER LOW

//EID<7:0>: Extended Identifier Bits <7:0>
//These bits hold the filter bits to be applied to the bits <7:0> of the Extended Identifier portion of
//a received message

#define MCPREG_RXM0SIDH      0X20//MASK 0 STANDARD IDENTIFIER HIGH
#define MCPREG_RXM1SIDH      0X24//MASK 1 STANDARD IDENTIFIER HIGH
//SID<10:3>: Standard Identifier Mask Bits <10:3>
//These bits hold the mask bits to be applied to bits <10:3> of the Standard Identifier portion of
//a received message

#define MCPREG_RXM0SIDL      0X21//MASK 0 STANDARD IDENTIFIER LOW
#define MCPREG_RXM1SIDL      0X25//MASK 1 STANDARD IDENTIFIER LOW

//bit 7-5 SID<2:0>: Standard Identifier Mask Bits <2:0>
//These bits hold the mask bits to be applied to bits<2:0> of the 
//Standard Identifier portion of a received message
//bit 1-0 EID<17:16>: Extended Identifier Mask Bits <17:16>
//These bits hold the mask bits to be applied to bits <17:16> of the
//Extended Identifier portion of a received message

#define MCPREG_RXM0EID8      0x22//MASK 0 EXTENDED IDENTIFIER HIGH
#define MCPREG_RXM1EID8      0x26//MASK 1 EXTENDED IDENTIFIER HIGH
//EID<15:8>: Extended Identifier Bits <15:8>
//These bits hold the filter bits to be applied to bits <15:8> of the
// Extended Identifier portion of a received message

#define MCPREG_RXM0EID0      0x23//MASK 0 EXTENDED IDENTIFIER LOW
#define MCPREG_RXM1EID1      0x27//MASK 1 EXTENDED IDENTIFIER LOW
//EID<7:0>: Extended Identifier Mask Bits <7:0>
//These bits hold the mask bits to be applied to the bits <7:0> of the 
//Extended Identifier portion of a received message

#define MCPREG_CNF1			0X2A//CONFIGURATION 1
#define CNF1TQ_4             0XC0
#define CNF1TQ_3             0X80
#define CNF1TQ_2             0X40
#define CNF1TQ_1             0X00
//bit 7-6 SJW<1:0>: Synchronization Jump Width Length
//11 = Length = 4 x TQ
//10 = Length = 3 x TQ
//01 = Length = 2 x TQ
//00 = Length = 1 x TQ
//bit 5-0 BRP<5:0>: Baud Rate Prescaler
//TQ = 2 x (BRP + 1) / FOSC

#define MCPREG_CNF2         0x29//CONFIGURATION 1
#define CNF2_BTLMODE        0X80
#define CNF2SAM_THREE       0X40
#define CNF2SAM_ONCE        0X00
//#define CNF2PRSEG
//bit 7 BTLMODE: Phase Segment 2 Bit Time Length
//1 = Length of Phase Seg 2 determined by PHSEG22:PHSEG20 bits of CNF3
//0 = Length of Phase Seg 2 is the greater of Phase Seg 1 and IPT (2TQ)
//bit 6 SAM: Sample Point Configuration
//1 = Bus line is sampled three times at the sample point
//0 = Bus line is sampled once at the sample point
//bit 5-3 PHSEG1<2:0>: Phase Segment 1 Length (PHSEG1 + 1) x TQ
//bit 2-0 PRSEG<2:0>: Propagation Segment Length (PRSEG + 1) x TQ

#define MCPREG_CNF3        0x28// CONFIGURATION 1
//bit 7 SOF: Start-of-Frame signal
//If CANCTRL.CLKEN = 1:
//1 = CLKOUT pin enabled for SOF signal
//0 = CLKOUT pin enabled for clockout function
//If CANCTRL.CLKEN = 0, bit 7 is don’t care.
//bit 6 WAKFIL: Wake-up Filter
//1 = Wake-up filter enabled
//0 = Wake-up filter disabled
//bit 2-0 PHSEG2<2:0>: Phase Segment 2 Length (PHSEG2 + 1) x TQ

#define MCPREG_TEC         0X1C//TRANSMIT ERROR COUNTER
#define MCPREG_REC         0X1D//RECEIVER ERROR COUNTER

#define MCPREG_EFLG        0X2D//ERROR FLAG
#define EFLG_RX1OVR			0X80//bit 7 RX1OVR: Receive Buffer 1 Overflow Flag
								//- Set when a valid message is received for RXB1 and CANINTF.RX1IF = 1
								//- Must be reset by MCU
#define EFLG_RX0OVR			0X40
//bit 6 RX0OVR: Receive Buffer 0 Overflow Flag
//- Set when a valid message is received for RXB0 and CANINTF.RX0IF = 1
//- Must be reset by MCU
#define EFLG_TXBO			0X20
//bit 5 TXBO: Bus-Off Error Flag
//- Bit set when TEC reaches 255
//- Reset after a successful bus recovery sequence

#define EFLG_TXEP			0X10
//bit 4 TXEP: Transmit Error-Passive Flag
//- Set when TEC is equal to or greater than 128
//- Reset when TEC is less than 128
#define EFLG_EXEP			0X08
//bit 3 RXEP: Receive Error-Passive Flag
//- Set when REC is equal to or greater than 128
//- Reset when REC is less than 128
#define EFLG_TXWAR			0X04
//bit 2 TXWAR: Transmit Error Warning Flag
//- Set when TEC is equal to or greater than 96
//- Reset when TEC is less than 96
#define EFLG_RWAR			0X02
//bit 1 RXWAR: Receive Error Warning Flag
//- Set when REC is equal to or greater than 96
//- Reset when REC is less than 96
#define EFLG_EWARN			0X01
//bit 0 EWARN: Error Warning Flag
//- Set when TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1)
//- Reset when both REC and TEC are less than 96

#define MCPREG_CANINTE      0X2B//INTERRUPT ENABLE
#define CANINTEBIT_MERRE    0X80//Message Error Interrupt Enable
//1 = Interrupt on error during message reception or transmission
//0 = Disabled
#define CANINTEBIT_WAKIE    0X40//Wakeup Interrupt Enable
//1 = Interrupt on CAN bus activity
//0 = Disabled
#define CANINTEBIT_ERRIE    0X20//Error Interrupt Enable (multiple sources in EFLG register)
//1 = Interrupt on EFLG error condition change
//0 = Disabled
#define CANINTEBIT_TX2IE    0X10//Transmit Buffer 2 Empty Interrupt Enable
//1 = Interrupt on TXB2 becoming empty
//0 = Disabled
#define CANINTEBIT_TX1IE    0X08//Transmit Buffer 1 Empty Interrupt Enable
//1 = Interrupt on TXB1 becoming empty
//0 = Disabled
#define CANINTEBIT_TX0IE    0x04//Transmit Buffer 0 Empty Interrupt Enable
//1 = Interrupt on TXB0 becoming empty
//0 = Disabled
#define CANINTEBIT_RX1IE    0X02//Receive Buffer 1 Full Interrupt Enable
//1 = Interrupt when message received in RXB1
//0 = Disabled
#define CANINTEBIT_RX0IE    0X01//Receive Buffer 0 Full Interrupt Enable
//1 = Interrupt when message received in RXB0
//0 = Disabled

#define MCPREG_CANINTF      0X2C//INTERRUPT FLAG
#define INTFBIT_MERRF    0X80//Message Error Interrupt Flag
//1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
//0 = No interrupt pending
#define INTFBIT_WAKIF    0X40//Wakeup Interrupt Flag
//1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
//0 = No interrupt pending
#define INTFBIT_ERRIF    0X20//Error Interrupt Flag (multiple sources in EFLG register)
//1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
//0 = No interrupt pending
#define INTFBIT_TX2IF    0X10//Transmit Buffer 2 Empty Interrupt Flag
//1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
//0 = No interrupt pending
#define INTFBIT_TX1IF    0X08//Transmit Buffer 1 Empty Interrupt Flag
//1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
//0 = No interrupt pending
#define INTFBIT_TX0IF    0X04//Transmit Buffer 0 Empty Interrupt Flag
//1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
//0 = No interrupt pending
#define INTFBIT_RX1IF    0X02//Receive Buffer 1 Full Interrupt Flag
//1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
//0 = No interrupt pending
#define INTFBIT_RX0IF    0X01//Receive Buffer 0 Full Interrupt Flag
//1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
//0 = No interrupt pending

#define MCPREG_CANCTRL   0X0F//CAN CONTROL REGISTER
#define CTRLBIT_REQOP    0XE0//Request Operation Mode
#define OPMODE_NORMAL    0X00
#define OPMODE_SLEEP     0X20
#define OPMODE_LOOPBK    0X40
#define OPMODE_LISTEN    0X60
#define OPMODE_CFG       0X80

//000 = Set Normal Operation Mode
//001 = Set Sleep Mode
//010 = Set Loopback Mode
//011 = Set Listen Only Mode
//100 = Set Configuration Mode
//All other values for REQOP bits are invalid and should not be used
//Note: On power-up, REQOP = b’111’
#define CTRLBIT_ABAT     0X10//Abort All Pending Transmissions
//1 = Request abort of all pending transmit buffers
//0 = Terminate request to abort all transmissions
#define CTRLBIT_OSM		0X08//One Shot Mode
//1 = Enabled. Message will only attempt to transmit one time
//0 = Disabled. Messages will re-attempt transmission, if required
#define CTRLBIT_CLKEN	0X04//CLKOUT Pin Enable
//1 = CLKOUT pin enabled
//0 = CLKOUT pin disabled (Pin is in high-impedance state)
#define CTRLBIT_CLKPRE   0X03//<1:0>: CLKOUT Pin Prescaler
//00 = FCLKOUT = System Clock/1
//01 = FCLKOUT = System Clock/2
//10 = FCLKOUT = System Clock/4
//11 = FCLKOUT = System Clock/8

#define MCPREG_CANSTAT   0X0E//CAN STATUS REGISTER
#define STATBITS_OPMOD   0XE0//Operation Mode
//bit 7-5
//000 = Device is in Normal Operation Mode
//001 = Device is in Sleep Mode
//010 = Device is in Loopback Mode
//011 = Device is in Listen Only Mode
//100 = Device is in Configuration Mode
//bit 4 Unimplemented: Read as '0'
#define STATBIT_ICOD     0X0E//Interrupt Flag Code
//bit 3-1
//000 = No Interrupt
//001 = Error Interrupt
//010 = Wake Up Interrupt
//011 = TXB0 Interrupt
//100 = TXB1 Interrupt
//101 = TXB2 Interrupt
//110 = RXB0 Interrupt
//111 = RXB1 Interrupt
#define STATRXB0E	0X06
//bit 0 Unimplemented: Read as '0'

#define MCPREG_RXB0D0	0X66
#define MCPREG_RXB0D1	0X67
#define MCPREG_RXB0D2	0X68
#define MCPREG_RXB0D3	0X69
#define MCPREG_RXB0D4	0X6A
#define MCPREG_RXB0D5	0X6B
#define MCPREG_RXB0D6	0X6C
#define MCPREG_RXB0D7	0X6D

#define MCPREG_RXB1D0	0X76
#define MCPREG_RXB1D1	0X77
#define MCPREG_RXB1D2	0X78
#define MCPREG_RXB1D3	0X79
#define MCPREG_RXB1D4	0X7A
#define MCPREG_RXB1D5	0X7B
#define MCPREG_RXB1D6	0X7C
#define MCPREG_RXB1D7	0X7D
#endif