sam7_emac.c
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C
609 行
/*
FreeRTOS V3.2.2 - Copyright (C) 2003-2005 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
* Basic interrupt driven driver for the EMAC peripheral. This driver is not
* reentrant as with uIP the buffers are only ever accessed from a single task.
*
* The simple buffer management used within uIP allows the EMAC driver to also
* be simplistic. The driver contained within the lwIP demo is more
* comprehensive.
*/
/* Standard includes. */
#include <string.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "semphr.h"
#include "task.h"
/* uIP includes. */
#include "uip.h"
/* Hardware specific includes. */
#include "emac.h"
#include "mii.h"
/* The buffer addresses written into the descriptors must be aligned so the
last few bits are zero. These bits have special meaning for the EMAC
peripheral and cannot be used as part of the address. */
#define emacADDRESS_MASK ( ( unsigned portLONG ) 0xFFFFFFFC )
/* Bit used within the address stored in the descriptor to mark the last
descriptor in the array. */
#define emacRX_WRAP_BIT ( ( unsigned portLONG ) 0x02 )
/* Bit used within the Tx descriptor status to indicate whether the
descriptor is under the control of the EMAC or the software. */
#define emacTX_BUF_USED ( ( unsigned portLONG ) 0x80000000 )
/* A short delay is used to wait for a buffer to become available, should
one not be immediately available when trying to transmit a frame. */
#define emacBUFFER_WAIT_DELAY ( 2 )
#define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )
/* Misc defines. */
#define emacINTERRUPT_LEVEL ( 5 )
#define emacNO_DELAY ( 0 )
#define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
#define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
/*-----------------------------------------------------------*/
/*
* Prototype for the EMAC interrupt asm wrapper.
*/
extern void vEMACISREntry( void );
/*
* Prototype for the EMAC interrupt function - called by the asm wrapper.
*/
__arm void vEMACISR( void );
/*
* Initialise both the Tx and Rx descriptors used by the EMAC.
*/
static void prvSetupDescriptors(void);
/*
* Write our MAC address into the EMAC. The MAC address is set as one of the
* uip options.
*/
static void prvSetupMACAddress( void );
/*
* Configure the EMAC and AIC for EMAC interrupts.
*/
static void prvSetupEMACInterrupt( void );
/*
* Some initialisation functions taken from the Atmel EMAC sample code.
*/
static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );
static portBASE_TYPE xGetLinkSpeed( void );
static portBASE_TYPE prvProbePHY( void );
/*-----------------------------------------------------------*/
/* Buffer written to by the EMAC DMA. Must be aligned as described by the
comment above the emacADDRESS_MASK definition. */
#pragma data_alignment=8
static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
/* Buffer read by the EMAC DMA. Must be aligned as described by he comment
above the emacADDRESS_MASK definition. */
#pragma data_alignment=8
static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
/* Descriptors used to communicate between the program and the EMAC peripheral.
These descriptors hold the locations and state of the Rx and Tx buffers. */
static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
/* The IP and Ethernet addresses are read from the uIP setup. */
const portCHAR cMACAddress[ 6 ] = { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 };
const unsigned char ucIPAddress[ 4 ] = { UIP_IPADDR0, UIP_IPADDR1, UIP_IPADDR2, UIP_IPADDR3 };
/* The semaphore used by the EMAC ISR to wake the EMAC task. */
static xSemaphoreHandle xSemaphore = NULL;
/*-----------------------------------------------------------*/
xSemaphoreHandle xEMACInit( void )
{
/* Code supplied by Atmel -------------------------------*/
/* Disable pull up on RXDV => PHY normal mode (not in test mode),
PHY has internal pull down. */
AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
/* Clear PB18 <=> PHY powerdown. */
AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, 1 << 18 );
AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, 1 << 18 );
/* After PHY power up, hardware reset. */
AT91C_BASE_RSTC->RSTC_RMR = ( AT91C_RSTC_KEY & ( ( unsigned ) 0xA5 << 24 ) ) | ( AT91C_RSTC_ERSTL & ( ( unsigned ) 0x0F << 8 ) );
AT91C_BASE_RSTC->RSTC_RCR = ( AT91C_RSTC_KEY & ( ( unsigned ) 0xA5 << 24 ) ) | AT91C_RSTC_EXTRST;
/* Wait for hardware reset end. */
while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
{
__asm( "NOP" );
}
/* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator). */
AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN;
/* End of code supplied by Atmel ------------------------*/
/* Wait for PHY auto init end (rather crude delay!). */
vTaskDelay( emacPHY_INIT_DELAY );
/* Setup the buffers and descriptors. */
prvSetupDescriptors();
/* Load our MAC address into the EMAC. */
prvSetupMACAddress();
/* Setup the pins. */
AT91F_EMAC_CfgPIO();
/* Try to connect. */
if( prvProbePHY() )
{
/* Enable the interrupt! */
prvSetupEMACInterrupt();
}
return xSemaphore;
}
/*-----------------------------------------------------------*/
portLONG lEMACSend( void )
{
static unsigned portBASE_TYPE uxTxBufferIndex = 0;
portBASE_TYPE xWaitCycles = 0;
portLONG lReturn = pdPASS;
portCHAR *pcBuffer;
/* Is a buffer available? */
while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
{
/* There is no room to write the Tx data to the Tx buffer. Wait a
short while, then try again. */
xWaitCycles++;
if( xWaitCycles > emacMAX_WAIT_CYCLES )
{
/* Give up. */
lReturn = pdFAIL;
break;
}
else
{
vTaskDelay( emacBUFFER_WAIT_DELAY );
}
}
/* lReturn will only be pdPASS if a buffer is available. */
if( lReturn == pdPASS )
{
/* Copy the headers into the Tx buffer. These will be in the uIP buffer. */
pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
/* If there is room, also copy in the application data if any. */
if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )
{
memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
}
/* Send. */
portENTER_CRITICAL();
{
if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
{
/* Fill out the necessary in the descriptor to get the data sent. */
xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
| AT91C_LAST_BUFFER
| AT91C_TRANSMIT_WRAP;
uxTxBufferIndex = 0;
}
else
{
/* Fill out the necessary in the descriptor to get the data sent. */
xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
| AT91C_LAST_BUFFER;
uxTxBufferIndex++;
}
AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
}
portEXIT_CRITICAL();
}
return lReturn;
}
/*-----------------------------------------------------------*/
unsigned portLONG ulEMACPoll( void )
{
static unsigned portBASE_TYPE ulNextRxBuffer = 0;
unsigned portLONG ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
portCHAR *pcSource;
/* Skip any fragments. */
while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
{
/* Mark the buffer as free again. */
xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
ulNextRxBuffer++;
if( ulNextRxBuffer >= NB_RX_BUFFERS )
{
ulNextRxBuffer = 0;
}
}
/* Is there a packet ready? */
while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
{
pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_LENGTH_FRAME;
if( ulSectionLength == 0 )
{
/* The frame is longer than the buffer pointed to by this
descriptor so copy the entire buffer to uIP - then move onto
the next descriptor to get the rest of the frame. */
if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
{
memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
ulLengthSoFar += ETH_RX_BUFFER_SIZE;
}
}
else
{
/* This is the last section of the frame. Copy the section to
uIP. */
if( ulSectionLength < UIP_BUFSIZE )
{
/* The section length holds the length of the entire frame.
ulLengthSoFar holds the length of the frame sections already
copied to uIP, so the length of the final section is
ulSectionLength - ulLengthSoFar; */
if( ulSectionLength > ulLengthSoFar )
{
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