📄 ctrlc2.mdl
字号:
Name "SW"
Location [49, 151, 488, 368]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "portrait"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "81"
Block {
BlockType Inport
Name "open"
Position [15, 58, 45, 72]
}
Block {
BlockType Inport
Name "vsw"
Position [25, 28, 55, 42]
Port "2"
}
Block {
BlockType Inport
Name "close"
Position [15, 203, 45, 217]
Port "3"
}
Block {
BlockType Gain
Name "1/Ron\n"
Position [215, 16, 255, 54]
Gain "100"
}
Block {
BlockType Clock
Name "Clock"
Position [20, 130, 40, 150]
Decimation "10"
}
Block {
BlockType Reference
Name "D Latch"
Ports [2, 2]
Position [165, 65, 210, 140]
SourceBlock "simulink_extras/Flip Flops/D Latch"
SourceType "DLatch"
}
Block {
BlockType Ground
Name "Ground"
Position [385, 65, 405, 85]
NamePlacement "alternate"
}
Block {
BlockType HitCross
Name "Hit \nCrossing"
Ports [1, 1]
Position [95, 115, 125, 145]
HitCrossingDirection "either"
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [2, 1]
Position [315, 77, 345, 108]
}
Block {
BlockType RelationalOperator
Name "Relational\nOperator"
Position [95, 57, 125, 88]
Operator "<="
}
Block {
BlockType RelationalOperator
Name "Relational\nOperator1"
Position [95, 202, 125, 233]
Operator ">"
}
Block {
BlockType Terminator
Name "Terminator"
Position [235, 110, 255, 130]
}
Block {
BlockType Switch
Name "select"
Position [425, 61, 465, 129]
Threshold "0.5"
}
Block {
BlockType Outport
Name "isw"
Position [500, 87, 530, 103]
}
Line {
SrcBlock "D Latch"
SrcPort 2
DstBlock "Terminator"
DstPort 1
}
Line {
SrcBlock "Hit \nCrossing"
SrcPort 1
Points [20, 0]
DstBlock "D Latch"
DstPort 2
}
Line {
SrcBlock "Ground"
SrcPort 1
DstBlock "select"
DstPort 1
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
DstBlock "select"
DstPort 2
}
Line {
SrcBlock "open"
SrcPort 1
DstBlock "Relational\nOperator"
DstPort 1
}
Line {
SrcBlock "Relational\nOperator1"
SrcPort 1
Points [155, 0; 0, -120]
DstBlock "Logical\nOperator"
DstPort 2
}
Line {
SrcBlock "close"
SrcPort 1
DstBlock "Relational\nOperator1"
DstPort 1
}
Line {
SrcBlock "select"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "isw"
DstPort 1
}
Branch {
Points [0, 90; -410, 0; 0, -55]
DstBlock "Hit \nCrossing"
DstPort 1
}
}
Line {
SrcBlock "vsw"
SrcPort 1
DstBlock "1/Ron\n"
DstPort 1
}
Line {
SrcBlock "1/Ron\n"
SrcPort 1
Points [110, 0; 0, 80]
DstBlock "select"
DstPort 3
}
Line {
SrcBlock "Clock"
SrcPort 1
Points [10, 0]
Branch {
Points [0, -60]
DstBlock "Relational\nOperator"
DstPort 2
}
Branch {
Points [0, 85]
DstBlock "Relational\nOperator1"
DstPort 2
}
}
Line {
SrcBlock "Relational\nOperator"
SrcPort 1
Points [20, 0]
DstBlock "D Latch"
DstPort 1
}
Line {
SrcBlock "D Latch"
SrcPort 1
DstBlock "Logical\nOperator"
DstPort 1
}
Annotation {
Name "Switch opens at first current zero followin"
"g t_open\nSwitch closes at t_close"
Position [369, 248]
ForegroundColor "blue"
FontSize 12
FontAngle "italic"
}
Annotation {
Name "BREAKER"
Position [361, 217]
ForegroundColor "red"
FontSize 14
}
}
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [110, 90, 130, 110]
ShowName off
IconShape "round"
Inputs "|+-"
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [325, 90, 345, 110]
ShowName off
IconShape "round"
Inputs "|+-"
}
Block {
BlockType Sin
Name "VIN"
Position [35, 85, 65, 115]
BackgroundColor "orange"
SineType "Time based"
Amplitude "120*sqrt(2)"
Frequency "2*pi*60"
SampleTime "0"
Port {
PortNumber 1
Name "vin"
TestPoint off
LinearAnalysisOutput off
LinearAnalysisInput off
RTWStorageClass "Auto"
DataLogging off
DataLoggingNameMode "SignalName"
DataLoggingDecimateData off
DataLoggingDecimation "2"
DataLoggingLimitDataPoints off
DataLoggingMaxPoints "5000"
}
}
Block {
BlockType Scope
Name "currents"
Ports [2]
Position [530, 212, 575, 283]
ForegroundColor "green"
NamePlacement "alternate"
Location [553, 495, 1131, 792]
Open on
NumInputPorts "2"
ZoomMode "yonly"
List {
ListType AxesTitles
axes1 "Breaker&load currents [A]"
axes2 "%<SignalLabel>"
}
List {
ListType SelectedSignals
axes1 ""
axes2 ""
}
TimeRange "0.25"
YMin "-10~-10"
YMax "10~10"
DataFormat "StructureWithTime"
}
Block {
BlockType SubSystem
Name "info"
Ports []
Position [38, 219, 99, 275]
ForegroundColor "darkGreen"
DropShadow on
ShowName off
TreatAsAtomicUnit off
MaskDisplay "plot(-1.5,-1.5,1.5,1.5,cos(0:.01:7),sin(0:.01:7"
") )\ndisp('Info')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "info"
Location [30, 156, 545, 415]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "110"
Annotation {
Name "RLC switched circuit"
Position [228, 17]
ForegroundColor "blue"
FontSize 12
FontWeight "bold"
}
Annotation {
Name " A series RL load in parallel with a capaci"
"tor operates under sinusoidal voltage\n excitation for a specified length of "
"time \"topen\" when, at the first subsequent \ncurrent zero, a circuit break"
"er connected between the source and the load\nsuddenly opens to reclose later"
" at a specified time \"tclose\". \nThe circuit breaker is simulated by means "
"of a switch block activated by a\nD latch flipflop block which determines a z"
"ero-crossing immediately following\nthe commanded time \"topen\". (To simulat"
"e the breaker opening at \"topen\" under\ncurrent chopping, simply delete the"
" portion involving the latch).\nReclosure takes place at time \"tclose\".\nTh"
"e source current isw as well as the load current iL and the capacitor voltag"
"e vC \nare exhibited as functions of time.\n"
Position [15, 35]
HorizontalAlignment "left"
VerticalAlignment "top"
FontSize 12
}
}
}
Block {
BlockType Constant
Name "tclose"
Position [35, 155, 65, 185]
BackgroundColor "orange"
Value ".155"
}
Block {
BlockType Constant
Name "topen"
Position [35, 15, 65, 45]
BackgroundColor "orange"
Value ".05"
}
Block {
BlockType Scope
Name "voltage"
Ports [1]
Position [560, 39, 605, 111]
ForegroundColor "green"
NamePlacement "alternate"
Location [554, 134, 1130, 431]
Open on
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "Input & capacitor voltages [V]"
}
List {
ListType SelectedSignals
axes1 ""
}
TimeRange "0.25"
YMin "-200"
YMax "200"
DataFormat "StructureWithTime"
}
Line {
Name "vin"
SrcBlock "VIN"
SrcPort 1
Points [15, 0]
Branch {
DstBlock "Sum"
DstPort 1
}
Branch {
Points [0, -55]
DstBlock "Mux"
DstPort 1
}
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "SW"
DstPort 2
}
Line {
SrcBlock "Sum1"
SrcPort 1
DstBlock "1/C"
DstPort 1
}
Line {
SrcBlock "1/C"
SrcPort 1
DstBlock "Integrator"
DstPort 1
}
Line {
Name "v_C"
SrcBlock "Integrator"
SrcPort 1
Points [15, 0]
Branch {
Points [0, 60]
Branch {
DstBlock "RLload"
DstPort 1
}
Branch {
Points [0, 45; -355, 0]
DstBlock "Sum"
DstPort 2
}
}
Branch {
Labels [1, 0]
DstBlock "Mux"
DstPort 2
}
}
Line {
Name "i_L"
Labels [0, 0]
SrcBlock "RLload"
SrcPort 1
Points [0, 0; -30, 0]
Branch {
DstBlock "Sum1"
DstPort 2
}
Branch {
Points [0, 105]
DstBlock "currents"
DstPort 2
}
}
Line {
SrcBlock "topen"
SrcPort 1
Points [80, 0; 0, 40]
DstBlock "SW"
DstPort 1
}
Line {
SrcBlock "tclose"
SrcPort 1
Points [80, 0; 0, -40]
DstBlock "SW"
DstPort 3
}
Line {
Name "isw"
Labels [0, 1]
SrcBlock "SW"
SrcPort 1
Points [0, 0; 20, 0]
Branch {
DstBlock "Sum1"
DstPort 1
}
Branch {
Points [0, 130]
DstBlock "currents"
DstPort 1
}
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "voltage"
DstPort 1
}
Annotation {
Name "vsw"
Position [150, 90]
}
Annotation {
Name "i_C"
Position [355, 93]
}
}
}
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