📄 dsk6713_mem.tci
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/*
* Copyright 2003 by Texas Instruments Incorporated.
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
*/
/* "@(#) ReferenceFrameworks 2.20.00.08 07-18-03 (swat-f02)" */
/*
* ======== Dsk6713_mem.tci ========
*
*
* This script simply sets up the BIOS MEM memory layout configuration
*/
/*
* Memory segments, their sizes, heaps, and heap sizes
* (SDRAM is external program memory, IRAM is internal memory)
* We split the 256K of internal RAM as 192K for code/data and 64K for cache.
* In internal and external data memory, we create heaps with names
* INTERNALHEAP and EXTERNALHEAP, respectively, and platform-independent
* portions of the application refer to these heaps by their names
* rather than the names of memory segments they are created in
* (as not all platforms have IRAM, SDRAM segments).
*/
/* Enable heap creation */
bios.enableMemoryHeaps(prog);
tibios.GBL.C621XCONFIGUREL2 = true; /* Enable L2 configuration */
tibios.GBL.C621XCCFGL2MODE = "4-way cache";
/* shorten the length of the IRAM section to allow 4-way cache */
tibios.IRAM.base = 0x00400;
tibios.IRAM.len = 0x2FC00; /* 192K - 1K */
tibios.IRAM.space = "code/data";
/* allocate heap named "INTERNALHEAP" of size 0x02000 in internal memory */
tibios.IRAM.createHeap = true;
tibios.IRAM.heapSize = 0x02000; /* 8K */
tibios.IRAM.enableHeapLabel = true;
tibios.IRAM.heapLabel = prog.extern( "INTERNALHEAP" );
/* allocate heap named "EXTERNALHEAP" of size 0x08000 in external memory */
tibios.SDRAM.createHeap = true;
tibios.SDRAM.heapSize = 0x08000; /* 32K */
tibios.SDRAM.enableHeapLabel = true;
tibios.SDRAM.heapLabel = prog.extern( "EXTERNALHEAP" );
/*
* add Memory Section for the boot loader asm code
* c621x/c671x/c64x ROM boot process copies 1Kb from CE1 to address 0
*/
var BOOTRAM = tibios.MEM.create("BOOTRAM");
BOOTRAM.comment = "Boot loader automatically fills this memory at startup";
BOOTRAM.base = 0x0;
BOOTRAM.len = 0x00000400;
BOOTRAM.createHeap = false;
BOOTRAM.space = "code/data";
/*
* Programmers Custom Boot Code section, which needs a separate section,
* in order to maintain control of where the section is placed in Flash
*/
var FLASHBOOT = tibios.MEM.create("FLASHBOOT");
FLASHBOOT.comment = "Flash memory for custom boot code";
FLASHBOOT.base = 0x90000000;
FLASHBOOT.len = 0x00000400;
FLASHBOOT.createHeap = false;
FLASHBOOT.space = "code/data";
/*
* Application code and initialized data sections that will be moved
* by custom boot routine as well as other initialized sections
* that we just keep in Flash that are not runtime critical.
*/
var FLASHREST = tibios.MEM.create("FLASHREST");
FLASHREST.comment = "Flash memory for other app initialized code/data";
FLASHREST.base = 0x90000400;
FLASHREST.len = 0x1FC00; /* FIXME : confirm size on dsk6713 */
FLASHREST.createHeap = false;
FLASHREST.space = "code/data";
/*
* Set the size of the application stack. Must be large
* enough to accomodate worst-case of nested priorities, if any.
*/
tibios.MEM.STACKSIZE = 0x0400;
// do placement of e.g. .text, .cinit, .bss etc in link.cmd
tibios.MEM.USERCOMMANDFILE = true;
// Set up Load & Run addresses of BIOS sections
tibios.MEM.ENABLELOADADDR = true;
// Now set runtime critical sections to be copied from Flash -> RAM
tibios.MEM.LOADBIOSSEG = FLASHREST;
tibios.MEM.BIOSSEG = tibios.IRAM; /* DSP/BIOS Code Section (.bios) */
tibios.MEM.LOADTRCDATASEG = FLASHREST;
tibios.MEM.TRCDATASEG = tibios.IRAM; /* TRC Initial Value (.trcdata) */
tibios.MEM.LOADHWIVECSEG = FLASHREST;
tibios.MEM.HWIVECSEG = tibios.IRAM; /* Int Service Table Mem (.hwi_vec) */
tibios.MEM.LOADRTDXTEXTSEG = FLASHREST;
tibios.MEM.RTDXTEXTSEG = tibios.IRAM; /* RTDX Text (.rtdx_text) */
// Now set other non-runtime-critical sections to load & run from Flash
tibios.MEM.LOADSYSINITSEG = FLASHREST;
tibios.MEM.SYSINITSEG = FLASHREST; /* Startup Code Section (.sysinit) */
tibios.MEM.LOADGBLINITSEG = FLASHREST;
tibios.MEM.GBLINITSEG = FLASHREST; /* DSP/BIOS Init Tables (.gblinit) */
/*
* Overriding default section placement
* assign listed sections to specified memory segments
*/
/* General */
/* BIOS code */
/* Compiler Sections */
/*
* .bss and .far segments should be in internal memory to avoid cache
* consistency problems with EDMA-ed data (it is by default,
* so this is more of a reminder)
*/
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