apcdef.h

Lucent的ATM处理套片APC驱动DEMO

/*******************************************************************************
 *
 * $Id: apcdef.h 1.50 2001/08/29 18:19:23 vikas1 RELEASED $
 *
 * Copyright 1996 - Lucent Technologies, Bell Labs  ALL RIGHTS RESERVED
 *
 ******************************************************************************/

#ifndef	_APCDEF_H
#define	_APCDEF_H

#include	"apcsys.h"

#define	SET_ALL			-1
#define	APC_NULL	0
#define	APC_ZERO	0

#define	LOW_BITS	0
#define	HIGH_BITS	1

/* used for OAM FM State (LUT3 OAM entry) */
#define	NORMAL		0x00
#define	I_FAULT		0x01
#define	AIS			0x02
#define	RDI			0x03

/* used for OAM FM State (IVT entry) */
#define	NORMAL		0x00
#define	I_FAULT		0x01
#define	E_FAULT		0x02
#define	P_FAULT		0x03

/* used for OAM FM Defect Type */
#define	FM_DEFAULT		0x00
#define	ATM_LAYER	0x01
#define	PHYS_LAYER	0x02
/* #define Reserved	0x11 */

/* used for OAM PM */
#define	LUTOAMSeg	0
#define	LUTOAME2E	1	/* As defined in PM Table */
#define	PM_SINK		0
#define	PM_SOURCE	1

/* used in apcbuf.c */
#define	APC_MAX_BRAM_SPACE	0x7FFFF
#define	APC_MAX_SPLIT_VC	0xC
#define	APC_MAX_VCINDEX	0xFFFF
#define	APC_MAX_CRAM_INDEX	0x1FFFF

/* used in apcconn.c */
#define	APC_NULL_VCX		0xFFFF
#define	APC_FWD_DIR		0
#define	APC_BWD_DIR		1
#define	ECT_DEF_RESERVED_VAL	0x7FFF8000
#define	ECT_WORD1_RESVD		0
#define	ECT_ABR_VD_WORD0	0x000001F0	/* for BRM consolidation, */
#define	ECT_ABR_VD_WORD1	0x1FF80000	/* init ER to max value   */
#define	F4_SEG_VCI		3
#define	F4_E2E_VCI		4
#define	ICT_WORD0_RESVD		0x7FFF8000
#define	ICT_WORD1_RESVD		0x7FFFFFFF
#define	NON_C_RVBR_RATE_PTR	0
#define	APC_VCI_3_4_NOR_OFFSET	-1
#define	APC_VCI_3_4_OAM_OFFSET	0
#define	ECT_SBIT_MASK		0xFFFFFFFE
#define	ECT_SBIT_SHFT		0x0

/* used in apcmulti.c */
#define	APC_NI_IS_UNI		0
#define	APC_DISBL_PMX		0
#define	APC_NI_IS_NNI		1
#define	NULL_MC_FILTER_PTR	0

/* used in apcinit.c */
#define	APC_NULL_RATE		APC_NULL	
#define	APC_PRAM_LAST_ENTRY	0x7FFFF
#define	APC_SET_RESVD		(0x1 << 21)
#define	APC_ESP_INTERVAL	16
#define	ING_EG_LUT_SHARE_CRAM	1
#define	ABR_RECMNDED_UPD_INTVL	0x100
#define	ABR_DEFAULT_AVTB_VAL	0x300

#define	APC_NUMOAMREGS		4
#define	APC_PMPROCESSES_MAX	127


#define APC_MAX_MPHY        32
#define APC_SCHED_BASE      0

#ifdef	NO_LUT_DYNAMIC
#define	APC_MAX_VPI		4096
#define	APC_MAX_VCI		65536
#else
#define	APC_MAX_VPI		2048	/* 4K overflows Eval Board memory */
#define	APC_MAX_VCI		32768	/* leave space for defrag & unused */
#endif
#define	APC_NUM_TI_PHY		16
#define	APC_MAX_ABR_MC		1024
#define	APC_MPHY		16
#define	APC_MAX_BG_INDEX	64
#define	APC_NUM_TYPE_II_PHY	16
#define	APC_TYPE_II_PHY_STRT	16
#define	APC_TYPE_II_PHY_END	32
#define	APC_ABR_INGRESS_PORT	31

#define	APC_FAB_A		0
#define	APC_FAB_B		1

#define	APC_POL_A		0
#define	APC_POL_B		1

/* The five rate classes */
enum
{
        CBR,
        RVBR,
        NVBR,
        ABR,
        UBR,
        MAX_CLASSES,
        XBR = 5,
        MAX_APC_EGRESS_CLASSES
}; 
#define	APC_POL_DISABLE		0
#define	APC_POL_CLP01_0T_1D	1
#define	APC_POL_CLP0_DROP	2
#define	APC_POL_CLP0_TAG	3
#define	APC_POL_CLP1_DROP	4	/* 5 - reserved */
#define	APC_POL_CLP01_DROP	6
#define	APC_POL_CLP01_TAG	7

#define	APC_INFIFO_CLAV		0x4
#define	APC_INFIFO_NFULL	0x10000000
#define	APC_INFIFO_FULL		1
#define	APC_INSREQ_PENDING	2

#define	APC_EGFIFO_CLAV		0x8
#define	APC_EGFIFO_NOCELL	16
#define	APC_ENABLE_CAPFIFO	0x80000000

#define	SETUP_MODE		1
#define	SEL_UPDATE_MODE		2
#define	OVERRIDE_MODE		3

#define	PARITY_CHECK		1
#define	NO_PARITY_CHECK		2

#define	APC_XMEM_COMP		1

#define	ODD_PARITY		0
#define	EVEN_PARITY		1

#define	SET_ENTRY		0
#define	GET_ENTRY		1

#define	INGRESS			0
#define	EGRESS			1

#define	LUT1_NOT_SET		0xFFFF
#define	APC_LUT1_VPBASE_MASK	0x1FFFF

#define	APC_VP_FLAG		1
#define	APC_VC_FLAG		0

#define	APC_DSBL_VC		0
#define	APC_ENBL_VC		1

#define	ADD_BRANCH		1
#define	DEL_BRANCH		0

#define	SUB_OP			0
#define	ADD_OP			1

#define	APC_LUCT_VALID_MASK	0x08000000
#define	APC_LUCT_VALID_SHIFT	27
#define	APC_LUCT_OFFSET_MASK	0x07c00000
#define	APC_LUCT_OFFSET_SHIFT	22

/* fabricPortBitmap bit 2 needs to be set for multicast
 * connections in dual APC mode */
#define	APC_DUAL_MODE_MC_PORT	2
#define	APC_LUT1_NNI			0x00200000
#define	APC_LUT1_OFFSET(offset)		((offset) << 22)
#define	APC_LUT1_MAXVPI(VPIBits)	((VPIBits) << 17)
#define	APC_LUT2_S_UNUSED		0x00200000
#define	APC_INVALID_VPBASE		0x1FFFF
#define	APC_LUT2_S_VPC			0x00200000
#define	APC_LUT2_MAXVCI(VCIBits)	((VCIBits) << 17)
#define	APC_LUT3_M_UNUSED		0x00010000
/* Maximum LUT2 and LUT3 sizes possible */
#define	APC_MAX_LUT2_SIZE		128*1024
#define	APC_MAX_LUT3_SIZE		128*1024

#define	APC_MAX_CBR_RATES		32
#define	APC_MAX_VBR_RATES		16
#define	APC_MAX_EPORT_RATES		32

/* Maximum number of rate representations allowed in APC for 
 * CBR, RVBR in ingress direction */
#define	APC_NUM_ICBR_RATES		32
#define	APC_NUM_IRVBR_RATES		16


#define APC_NUM_FABRIC_PORTS        40

/* Maximum number of rate representations allowed in APC for
 * CBR, RVBR in egress direction */
#define	APC_NUM_ECBR_RATES		32
#define	APC_NUM_ERVBR_RATES		16

#define	APC_BGLOCK_ENABLED		0
#define	APC_ULPBK_DISBL			0
#define	TS_DELAY			0x100

#define	STAT1_L1BZ_ERROR	0x00400000	/* lut1 address busy */
#define	STAT1_L2BZ_ERROR	0x00200000	/* lut2 address busy */
#define	STAT1_CNMT_ERROR	0x00100000	/* cap fifo not empty */
#define	STAT1_INNF_ERROR	0x00080000	/* ing insertion fifo not full */
#define	STAT1_IFBP_ERROR	0x00040000	/* ing fab BP exceeded */
#define	STAT1_EMQC_ERROR	0x00020000	/* CBR egr multicast q is full */
#define	STAT1_EMQR_ERROR	0x00010000	/* RVBR egr multicast q is full */
#define	STAT1_EMQN_ERROR	0x00008000	/* NVBR egr multicast q is full */
#define	STAT1_EMQA_ERROR	0x00004000	/* ABR egr multicast q is full */
#define	STAT1_EMQU_ERROR	0x00002000	/* UBR egr multicast q is full */
#define	STAT1_PMSQ_ERROR	0x00001000	/* PM sequencing err */
#define	STAT1_IIQF_ERROR	0x00000800	/* ingr ins q almost full */
#define	STAT1_EIQF_ERROR	0x00000400	/* egr ins q almost full */
#define	STAT1_FMFI_ERROR	0x00000200	/* fm fifo intr bit */
#define	STAT1_FMOV_ERROR	0x00000100	/* fm fifo over flow */
#define	STAT1_USUP_ERROR	0x00000080	/* unsupported oam cell */
#define	STAT1_UDEF_ERROR	0x00000040	/* undefined oam cell */
#define	STAT1_IIVL_ERROR	0x00000020	/* recd cell invalid vpi/vci */
#define	STAT1_IIAC_ERROR	0x00000010	/* recd cell for ing inact conn */
#define	STAT1_EIAC_ERROR	0x00000008	/* recd cell for eg inact conn */
#define	STAT1_PIVL_ERROR	0x00000004	/* recd cell with invalid pti */
#define	STAT1_PCRC_ERROR	0x00000002	/* payload crc error */

#define	APC_STAT1_ERROR	(STAT1_L1BZ_ERROR|\
			STAT1_L2BZ_ERROR|STAT1_CNMT_ERROR|STAT1_INNF_ERROR|\
			STAT1_IFBP_ERROR|STAT1_EMQC_ERROR|STAT1_EMQR_ERROR|\
			STAT1_EMQN_ERROR|STAT1_EMQA_ERROR|STAT1_EMQU_ERROR|\
			STAT1_PMSQ_ERROR|STAT1_IIQF_ERROR|STAT1_EIQF_ERROR|\
			STAT1_FMFI_ERROR|STAT1_FMOV_ERROR|STAT1_USUP_ERROR|\
			STAT1_UDEF_ERROR|STAT1_IIVL_ERROR|STAT1_IIAC_ERROR|\
			STAT1_EIAC_ERROR|\
			STAT1_PIVL_ERROR|STAT1_PCRC_ERROR)

#define	STAT2_CLKC_ERROR	0x00010000	/* clock status change */
#define	STAT2_ICBF_ERROR	0x00008000	/* ing cell buffer full */
#define	STAT2_ECBF_ERROR	0x00004000	/* eg cell buffer full */
#define	STAT2_VFIB_ERROR	0x00002000	/* protocol vio on fab i/f B */
#define	STAT2_VFIA_ERROR	0x00001000	/* protocol vio on fab i/f A */
#define	STAT2_VUTB_ERROR	0x00000800	/* protocol vio on tx u_B */
#define	STAT2_VURB_ERROR	0x00000400	/* protocol vio on rx u_B */
#define	STAT2_VUTA_ERROR	0x00000200	/* protocol vio on tx u_A */
#define	STAT2_VURA_ERROR	0x00000100	/* protocol vio on rx u_A */
#define	STAT2_FABB_ERROR	0x00000080	/* par error on fab i/f B */
#define	STAT2_FABA_ERROR	0x00000040	/* par error on fab i/f A */
#define	STAT2_UTPB_ERROR	0x00000020	/* par error on U_B */
#define	STAT2_UTPA_ERROR	0x00000010	/* par error on U_A */
#define	STAT2_PRAM_ERROR	0x00000008	/* pram error */
#define	STAT2_BRAM_ERROR	0x00000004	/* bram error */
#define	STAT2_VRAM_ERROR	0x00000002	/* vcram error */
#define	STAT2_CRAM_ERROR	0x00000001	/* cram error */

#define	APC_STAT2_ERROR	(STAT2_CLKC_ERROR|STAT2_ICBF_ERROR|\
			STAT2_ECBF_ERROR|STAT2_VFIB_ERROR|STAT2_VFIA_ERROR|\
			STAT2_VUTB_ERROR|STAT2_VURB_ERROR|STAT2_VUTA_ERROR|\
			STAT2_VURA_ERROR|STAT2_FABB_ERROR|STAT2_FABA_ERROR|\
			STAT2_UTPB_ERROR|STAT2_UTPA_ERROR|STAT2_PRAM_ERROR|\
			STAT2_BRAM_ERROR| \
			STAT2_VRAM_ERROR| \
			STAT2_CRAM_ERROR)

#define	STAT3_IIRQ_FULL		0x00000400	/* ing insert queue full */
#define	STAT3_IIQ_EMPTY		0x00000200	/* ing insert queue empty */
#define	STAT3_EIRQ_FULL		0x00000100	/* eg insert queue full */
#define	STAT3_EIQ_EMPTY		0x00000080	/* eg insert queue empty */
#define	STAT3_FMF_AFULL		0x00000040	/* fm fifo almost full */
#define	STAT3_FMFI_FULL		0x00000020	/* fm fifo full */
#define	STAT3_FMF_NOTMT		0x00000010	/* fm fifo not empty */
#define	STAT3_CAPF_CLAV		0x00000008	/* cap fifo cell available */
#define	STAT3_INSF_CLAV		0x00000004	/* ins fifo cell available */
#define	STAT3_CLK_STS_B		0x00000002	/* clock status B */
#define	STAT3_CLK_STS_A		0x00000001	/* clock status A */

/* For ICT and VCT Words */
#define	MAX_ICT_WORDS 2
#define	MAX_ECT_WORDS 2   

/* For RM Cell Format specified in ADS */
#define	RM_CELL_SHIFT_EXPONENT 	9
#define	RM_CELL_SHIFT_NZ 	14

#endif