📄 drv_1215.h
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/************************************************************************
* *
* Copyright (C) SEIKO EPSON CORP. 2002 *
* *
* File name: Drv_LCD.h *
* This is pson S1D13706 LCD controller driver head file for *
* L1F01215T13 under Epson E0C33000 platform. *
* *
* *
* Revision history *
* 2002-7-19 Andrew Yin Start. *
* *
************************************************************************/
#define _DEBUG_VERSION
#ifndef true
#define true 1
#define false 0
#endif
#ifndef TRUE
#define TRUE 1
#define FALSE 0
#endif
// REGISTER_OFFSET points to the starting address of the S1D13706 registers
#define REGISTER_OFFSET 0x400000 // 0x4000000-0x403ffff 256k is enough
// DISP_MEM_OFFSET points to the starting address of the display buffer memory
#define DISP_MEM_OFFSET 0x440000
// DISP_MEMORY_SIZE is the size of display buffer memory : SRAM
#define DISP_MEMORY_SIZE 0x14000 /* 80K */
#define LCD_POWERDOWN_TIME 1200 /* Time before LCD loses power (in milliseconds) */
#define LCD_POWERUP_TIME 50 /* Time before LCD gets power (in milliseconds) */
#define LCD_SOLUTION_WIDTH 320
#define LCD_SOLUTION_HEIGHT 240
#define ONE_LINE_BYTE_NUMBER 160
#define ONE_LINE_SHORT_NUMBER 80
#define BPP 4
// S1D13706 register name and corresponding offset address
#define REG_REVISION_CODE 0x00
#define REG_DISP_BUFFER_SIZE 0x01
#define REG_CONFIG_READBACK 0x02
#define REG_BUSCLK_MEMCLK_CONFIG 0x04
#define REG_PCLK_CONFIG 0x05
#define REG_LUT_BLUE_WRITE_DATA 0x08
#define REG_LUT_GREEN_WRITE_DATA 0x09
#define REG_LUT_RED_WRITE_DATA 0x0a
#define REG_LUT_WRITE_ADDR 0x0b
#define REG_LUT_BLUE_READ_DATA 0x0c
#define REG_LUT_GREEN_READ_DATA 0x0d
#define REG_LUT_RED_READ_DATA 0x0e
#define REG_LUT_READ_ADDR 0x0f
#define REG_PANEL_TYPE 0x10
#define REG_MOD_RATE 0x11
#define REG_HORIZ_TOTAL 0x12
#define REG_HDP 0x14
#define REG_HDP_START_POS0 0x16
#define REG_HDP_START_POS1 0x17
#define REG_VERT_TOTAL0 0x18
#define REG_VERT_TOTAL1 0x19
#define REG_VDP0 0x1c
#define REG_VDP1 0x1d
#define REG_VDP_START_POS0 0x1e
#define REG_VDP_START_POS1 0x1f
#define REG_HSYNC_PULSE_WIDTH 0x20
#define REG_HSYNC_PULSE_START_POS0 0x22
#define REG_HSYNC_PULSE_START_POS1 0x23
#define REG_VSYNC_PULSE_WIDTH 0x24
#define REG_VSYNC_PULSE_START_POS0 0x26
#define REG_VSYNC_PULSE_START_POS1 0x27
#define REG_DTFD_GCP_INDEX 0x28
#define REG_DTFD_GCP_DATA 0x2c
#define REG_DISPLAY_MODE 0x70
#define REG_SPECIAL_EFFECTS 0x71
#define REG_MAIN_WIN_DISP_START_ADDR0 0x74
#define REG_MAIN_WIN_DISP_START_ADDR1 0x75
#define REG_MAIN_WIN_DISP_START_ADDR2 0x76
#define REG_MAIN_WIN_ADDR_OFFSET0 0x78
#define REG_MAIN_WIN_ADDR_OFFSET1 0x79
#define REG_SUB_WIN_DISP_START_ADDR0 0x7c
#define REG_SUB_WIN_DISP_START_ADDR1 0x7d
#define REG_SUB_WIN_DISP_START_ADDR2 0x7e
#define REG_SUB_WIN_ADDR_OFFSET0 0x80
#define REG_SUB_WIN_ADDR_OFFSET1 0x81
#define REG_SUB_WIN_X_START_POS0 0x84
#define REG_SUB_WIN_X_START_POS1 0x85
#define REG_SUB_WIN_Y_START_POS0 0x88
#define REG_SUB_WIN_Y_START_POS1 0x89
#define REG_SUB_WIN_X_END_POS0 0x8c
#define REG_SUB_WIN_X_END_POS1 0x8d
#define REG_SUB_WIN_Y_END_POS0 0x90
#define REG_SUB_WIN_Y_END_POS1 0x91
#define REG_POWER_SAVE_CONFIG 0xa0
#define REG_CPU_ACCESS_CONTROL 0xa1
#define REG_SOFTWARE_RESET 0xa2
#define REG_BIG_ENDIAN_SUPPORT 0xa3
#define REG_SCRATCH_PAD0 0xa4
#define REG_SCRATCH_PAD1 0xa5
#define REG_GPIO_CONFIG0 0xa8
#define REG_GPIO_CONFIG1 0xa9
#define REG_GPIO_STATUS_CONTROL0 0xac
#define REG_GPIO_STATUS_CONTROL1 0xad
#define REG_PWM_CV_CLOCK_CONTROL 0xb0
#define REG_PWM_CV_CLOCK_CONFIG 0xb1
#define REG_CV_CLOCK_BURST_LENGTH 0xb2
#define REG_PWM_CLOCK_DUTY_CYCLE 0xb3
#define FINISHED_REG_CFG 0xff
#define MACRO_ENABLE_BLANK_DISPLAY() { *(ucpRegBaseAddr + REG_DISPLAY_MODE ) |= 0x80; }
#define MACRO_DISABLE_BLANK_DISPLAY() { *(ucpRegBaseAddr + REG_DISPLAY_MODE ) &= ~0x80; }
#define MACRO_ENABLE_LCD_PANEL() { *(ucpRegBaseAddr + REG_GPIO_STATUS_CONTROL0 ) |= 0x10; }
#define MACRO_DISABLE_LCD_PANEL() { *(ucpRegBaseAddr + REG_GPIO_STATUS_CONTROL0 ) &= ~0x10; }
#define MACRO_INTO_POWER_SAVE_MODE() { *(ucpRegBaseAddr + REG_POWER_SAVE_CONFIG |= 0x01;}
#define MACRO_INTO_POWER_NORMAL_MODE() { *(ucpRegBaseAddr + REG_POWER_SAVE_CONFIG &= ~0x01;}
typedef struct RegInitItem
{
unsigned short ushIndex;
unsigned char uchValue;
}REG_INIT_ITEM;
REG_INIT_ITEM S1D13706Mode[] = {
{REG_BUSCLK_MEMCLK_CONFIG ,0x00}, // Reg 4h
// BCLK to MCLK is 1:1
{REG_PCLK_CONFIG ,0x12}, // Reg 5h
/* source of PCLK is CLK1 and PCLK Source to PCLK Frequency Ratio is 2:1
, in such configuration ,the output frame freq is about 75Hz */
{REG_PANEL_TYPE ,0x00}, // Reg 10h
// Mono Panel , Passive Panel 4-bit, Panel Type: STN
{REG_MOD_RATE ,0x00}, // Reg 11h
// the MOD output signal (DRDY) toggles every FPFRAME
{REG_HORIZ_TOTAL ,0x30}, // Reg 12h
// (0x30+1)*8 = 392; 392*255*75*2 = 14994000 while our CLK1 is 15M
{REG_HDP ,0x27}, // Reg 14h
// (0x27+1)*8 = 320
{REG_HDP_START_POS0 ,0x00}, // Reg 16h
{REG_HDP_START_POS1 ,0x00}, // Reg 17h
// For passive LCD panels these bits must be set to 00h which will result in HDPS = 22
{REG_VERT_TOTAL0 ,0x0FE}, // Reg 18h
{REG_VERT_TOTAL1 ,0x00}, // Reg 19h
// 0xfe +1 = 255
{REG_VDP0 ,0xef}, // Reg 1ch
{REG_VDP1 ,0x00}, // Reg 1dh
// 0xef +1 = 240
{REG_VDP_START_POS0 ,0x00}, // Reg 1eh
{REG_VDP_START_POS1 ,0x00}, // Reg 1fh
// For passive LCD panels these bits must be set to 00h
{REG_HSYNC_PULSE_WIDTH ,0x87}, // Reg 20h
// For passive panels, bit 7 must be set to 1. and real pulse width is 7+1 = 8 pixel
{REG_HSYNC_PULSE_START_POS0 ,0x00}, // Reg 22h
{REG_HSYNC_PULSE_START_POS1 ,0x00}, // Reg 23h
// 0+1 =1 real start position is 1
{REG_VSYNC_PULSE_WIDTH ,0x80}, // Reg 24h
// For passive panels, bit7 must be set to 1.
{REG_VSYNC_PULSE_START_POS0 ,0x01}, // Reg 26h
{REG_VSYNC_PULSE_START_POS1 ,0x00}, // Reg 27h
// For passive panels, these bits must be set to 00h
{REG_DISPLAY_MODE ,0x82}, // Reg 70h //0x80 is 1bpp 0x81 is 2bpp 0x82 is 4bpp
// display is still blank at this time dithering is enabled for passive LCD panels depth is 1bpp.
{REG_SPECIAL_EFFECTS ,0x00}, // Reg 71h
// no Special Effects are used at first
{REG_MAIN_WIN_DISP_START_ADDR0 ,0x00}, // Reg 74h
{REG_MAIN_WIN_DISP_START_ADDR1 ,0x00}, // Reg 75h
{REG_MAIN_WIN_DISP_START_ADDR2 ,0x00}, // Reg 76h
// our main window starts from address zero
{REG_MAIN_WIN_ADDR_OFFSET0 ,0x28}, // Reg 78h //0x0a is 1bpp, 0x14 is 2bpp 0x28 is 4bpp
{REG_MAIN_WIN_ADDR_OFFSET1 ,0x00}, // Reg 79h
// 160width *16bpp / 8 / 4 = 0x50
{REG_SUB_WIN_DISP_START_ADDR0 ,0x00}, // Reg 7ch
{REG_SUB_WIN_DISP_START_ADDR1 ,0x00}, // Reg 7dh
{REG_SUB_WIN_DISP_START_ADDR2 ,0x00}, // Reg 7eh
{REG_SUB_WIN_ADDR_OFFSET0 ,0x50}, // Reg 80h
{REG_SUB_WIN_ADDR_OFFSET1 ,0x00}, // Reg 81h
{REG_SUB_WIN_X_START_POS0 ,0x00}, // Reg 84h
{REG_SUB_WIN_X_START_POS1 ,0x00}, // Reg 85h
{REG_SUB_WIN_Y_START_POS0 ,0x00}, // Reg 88h
{REG_SUB_WIN_Y_START_POS1 ,0x00}, // Reg 89h
{REG_SUB_WIN_X_END_POS0 ,0x4f}, // Reg 8ch
{REG_SUB_WIN_X_END_POS1 ,0x00}, // Reg 8dh
{REG_SUB_WIN_Y_END_POS0 ,0xef}, // Reg 90h
{REG_SUB_WIN_Y_END_POS1 ,0x00}, // Reg 91h
// no sub window is used at first */
{REG_POWER_SAVE_CONFIG ,0x00}, // Reg a0h
// the software initiated power save mode is disabled
{REG_CPU_ACCESS_CONTROL ,0x00}, // Reg a1h
{REG_SOFTWARE_RESET ,0x00}, // Reg a2h
{REG_BIG_ENDIAN_SUPPORT ,0x00}, // Reg a3h
{REG_SCRATCH_PAD0 ,0x00}, // Reg a4h
{REG_SCRATCH_PAD1 ,0x00}, // Reg a5h
{REG_GPIO_CONFIG0 ,0x00}, // Reg a8h
{REG_GPIO_CONFIG1 ,0x00}, // Reg a9h
// in our case, since cnf3 is set to 0 , REG_GPIO_CONFIG has no effect
{REG_GPIO_STATUS_CONTROL0 ,0x00}, // Reg ach
{REG_GPIO_STATUS_CONTROL1 ,0x00}, // Reg adh
// in our case, only GPIO4 is used as LCD enable first disable LCD.
{REG_PWM_CV_CLOCK_CONTROL ,0x00}, // Reg b0h
{REG_PWM_CV_CLOCK_CONFIG ,0x00}, // Reg b1h
{REG_CV_CLOCK_BURST_LENGTH ,0x00}, // Reg b2h
{REG_PWM_CLOCK_DUTY_CYCLE ,0x00}, // Reg b3h
// PWM and CV are not used in our case
{FINISHED_REG_CFG, 0x00}
};
unsigned char *ucpRegBaseAddr = (unsigned char*)REGISTER_OFFSET ;
unsigned char *ucpMemBaseAddr = (unsigned char*)DISP_MEM_OFFSET ;
unsigned short *uspMemBaseAddr = (unsigned short*)DISP_MEM_OFFSET;
#define S1D_WRITE_PALETTE( p, i, r, g, b ) \
{ \
((volatile unsigned char*)( p ))[ 0x0A ] = ( unsigned char )(( r )); \
((volatile unsigned char*)( p ))[ 0x09 ] = ( unsigned char )(( g )); \
((volatile unsigned char*)( p ))[ 0x08 ] = ( unsigned char )(( b )); \
((volatile unsigned char*)( p ))[ 0x0B ] = ( unsigned char )( i ); \
}
#define S1D_READ_PALETTE( p, i, r, g, b ) \
{ \
((volatile unsigned char*)( p ))[ 0x0F ] = ( unsigned char )( i ); \
r = ((volatile unsigned char*)( p ))[ 0x0E ]; \
g = ((volatile unsigned char*)( p ))[ 0x0D ]; \
b = ((volatile unsigned char*)( p ))[ 0x0C ]; \
}⌨️ 快捷键说明
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