crti.s90

startup code has configured Timer0

;*******************************************************************
;  startup.s90 for interrupt enabled AVR micro 8515.
;
; This module can be edited as required to support interrupt routines.
; As supplied it will enable a 25mS interrupt using Timer0 and around
; a 70 mS watchdog timer timeout. The C code can use the I_Timer byte
; in sram to synchronise with the clock tick, either specifically or
; via some task despatcher. In this version the WDT is not activated.
;
;
;
; Revision History
;  1  - Pushed r16 before use in interrupts.
;
;
; Ron Kreymborg
;*******************************************************************

	col	120
	lstexp-				; no macro listing

#include "avr.inc"
#include "io8515.h"


;*****************************************************************
; General constants

CLKTICK=	25000			; 25uSec tick for clock0
CLOCK=		256-(CLKTICK*4/1024)	; 4mHZ, 1024 divider


extern		_CTimer0

;*******************************************************************
; CODE SEGMENT

	name	startup
	rseg	scode
	extern	SOFTSTK, HARDSTK
	extern	_main
	

	rjmp    _prep

; Interrupt vectors

	rjmp    ext_int0
	rjmp    ext_int1
	rjmp    tim1_capt
	rjmp    tim1_compa
	rjmp    tim1_compb
	rjmp    tim1_ovf
	rjmp    tim0_ovf
	rjmp    spi_handler
	rjmp    uart_rxc
	rjmp    uart_dre
	rjmp    uart_txc
	rjmp    ana_comp


;*****************************************************************
; Main routine starts

_prep	ldiz	HARDSTK
	out	SPH,r31
	out     SPL,r30
	rcall	_init
	rcall	_rmclr
	ldiy	SOFTSTK+1
	sei				; hello world
	rcall	_main
	rjmp	$


_rmclr	clr	r27
	sbiw	r30,1
_rcl1	st	-z,r27
	cpi	r30,$60
	brne	_rcl1
	tst	r31
	brne	_rcl1
	ret
	





;******************************************************************************
; Machine once only initialisation sequence.
;******************************************************************************

_init	ldi	r17,$1f			; trick to disable WDT
	out	WDTCR,r17
	ldi	r17,$12			; set for 64mS WDT when eventually enabled
	out	WDTCR,r17

	ldi	r17,$40
	out	GIMSK,r17
	ldi	r17,$02
	out	TIMSK,r17
	sei
	nop
	nop
	nop
	nop
	nop
	cli
	ldi	r17,$00
	out	TIMSK,r17
	ldi	r17,$00
	out	GIMSK,r17

; By now any bogus reset created interrupts have been cleared, so
; can now get on with initialising the machine.
; Initialise the ports

	ser	r17			; A,B,C & D all outputs
	out	DDRA,r17
	out	DDRB,r17
	out	DDRC,r17
	out	DDRD,r17

; Ensure unused interrupts are disabled

	ldi	r17,$90			; disable analog comparator
	out	ACSR,r17
	ldi	r17,$00			; disable uart
	out	UCR,r17
	ldi	r17,$1b			; disable SPI
	out	SPCR,r17
	ldi	r17,$00			; set eeprom inactive
	out	EECR,r17
	ldi	r17,$02			; setup the MCU register
	out	MCUCR,r17

; Setup the uart for 2400 baud.

	ldi	r17,103			; 2400 baud @ 4Mhz
	out	UBRR,r17
	ldi	r17,$d8		; enable receiver & transmitter
	out	UCR,r17

; Set Timer0 running. This ticks at CLKTICK uSec intervals. Note
; relationship defining CLKTICK in uS depends on 1024 prescalar.

	ldi	r17,$05		; set prescalar (1024)
	out	TCCR0,r17
	ldi	r17,CLOCK	; load derived constant
	out	TCNT0,r17
	ldi	r17,$02		; enable timer0 interrupts
	out	TIMSK,r17

; Preset timer1 to run at CLK/1024. 

	ldi	r17,$05
	out	TCCR1B,r17

; Enable the watchdog timer.

	ldi	r17,$0a		; run at around 70mS
;	out	WDTCR,r17		; enable WD interrupts

	ret				; note interrupts NOT enabled




;************************************************************************
; Interrupt routines
;************************************************************************

ext_int0:
	push	r16
	in      r16,SREG
	push	r16
	in      r16,GIMSK
	andi    r16,$bf
	out     GIMSK,r16
	pop	r16
	out     SREG,r16
	pop	r16
	reti

;************************************************************************

ext_int1:
	push	r16
	in      r16,SREG
	push	r16
	in      r16,GIMSK
	andi    r16,$7f
	out     GIMSK,r16
	pop	r16
	out     SREG,r16
	pop	r16
	reti

;************************************************************************

tim1_capt:
	push	r16
	in      r16,SREG
	push	r16
	in      r16,TIMSK
	andi    r16,$F7
	out     TIMSK,r16
	pop	r16
	out     SREG,r16
	pop	r16
	reti

;************************************************************************

tim1_compa:
	push	r16
	in      r16,SREG
	push	r16
	in      r16,TIMSK
	andi    r16,$bf
	out     TIMSK,r16
	pop	r16
	out     SREG,r16
	pop	r16
	reti

;************************************************************************

tim1_compb:
	push	r16
	in      r16,SREG
	push	r16
	in      r16,TIMSK
	andi    r16,$df
	out     TIMSK,r16
	pop	r16
	out     SREG,r16
	pop	r16
	reti

;************************************************************************
; Timer1 overflow. Clear any reversing bits.

tim1_ovf:
	push	r16
	in      r16,SREG
	push	r16
	in	r16,TIMSK		; disable timer1 interrupts
	cbr	r16,$80
	out	TIMSK,r16
	pop	r16
	out     SREG,r16
	pop	r16
	reti

;********************************************************************
; TIMER0 interrupt. This runs at CLKTICK millisecs.

tim0_ovf
	rjmp	_CTimer0
	push	r16
	in      r16,SREG		; save status
	push	r16
	ldi	r16,CLOCK		; reload tick
	out	TCNT0,r16
	ldi	r16,0x01		; set wake up flag
	sts	_I_Time,r16
	pop	r16
	out     SREG,r16		; restore status
	pop	r16
	reti

;************************************************************************

spi_handler:
	push	r16
	in      r16,SREG
	push	r16
	ldi     r16,$3f
	out     SPCR,r16
	pop	r16
	out     SREG,r16
	pop	r16
	reti

;************************************************************************
; UART RX interrupt.

uart_rxc:
	push	r16
	in      r16,SREG		; save SREG
	out     SREG,r16
	pop	r16
	reti

;************************************************************************

uart_dre:
	push	r16
	in      r16,SREG
	out     SREG,r16
	pop	r16
	reti

;************************************************************************
; UART TX interrupt.

uart_txc:
	push	r16
	in      r16,SREG
	out     SREG,r16
	pop	r16
	reti

;************************************************************************

ana_comp:
	push	r16
	in      r16,SREG
	push	r16
	ldi     r16,$83
	out     ACSR,r16
	pop	r16
	out     SREG,r16
	pop	r16
	ret


;************************************************************************
; DATA SEGMENT IN SRAM
;************************************************************************

	rseg	sdata			; data segment
	public	_I_Time			; so C can get at it
	
_I_Time	ds	1			; 2 byte integer

	end