📄 39vf400.lst
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TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Thu Dec 8 11:06:36 2005
Copyright (c) 1987-1999 Texas Instruments Incorporated
39vf400.asm PAGE 6
271 000f 8aa0 POPD *+
272 0010 80a0 SAR AR0,*+
273 0011 8180 SAR AR1,*
274 0012 b006 LARK AR0,6
275 0013 00ea LAR AR0,*0+,AR2
276
277 .sym _Temp,1,30,1,16
278 .sym _Temp1,2,30,1,16
279 .sym _SST_id1,3,14,1,16
280 .sym _SST_id2,4,14,1,16
281 .sym _ReturnStatus,5,14,1,16
282 .line 9
283 ;>>>> cs_flash_0;
284 0014 bf80 LACK 64511
0015 fbff
285 0016 bc00! LDPK _MCRC
286 0017 6e00! AND _MCRC
287 0018 9000! SACL _MCRC
288 0019 bf80 LACK 1024
001a 0400
289 001b bc00! LDPK _PFDATDIR
290 001c 6d00! OR _PFDATDIR
291 001d 9000! SACL _PFDATDIR
292 001e bf80 LACK 65531
001f fffb
293 0020 6e00! AND _PFDATDIR
294 0021 9000! SACL _PFDATDIR
295 .line 10
296 ;>>>> Temp1 = (uint *)(BaseAddr+0x5555); //address 5555h
297 0022 b202 LARK AR2,2
298 0023 8be0 MAR *0+
299 0024 ae80 SPLK #54613,*
0025 d555
300 .line 11
301 ;>>>> *Temp1= 0xAA; // write 0xAAAA
302 0026 038b LAR AR3,* ,AR3
303 0027 b9aa LACK 170
304 0028 908a SACL * ,AR2
305 .line 13
306 ;>>>> Temp1 = (uint *)(BaseAddr+0x2AAA); //address 2AAAh
307 0029 ae80 SPLK #43690,*
002a aaaa
308 .line 14
309 ;>>>> *Temp1= 0x55; // write 0x5555
310 002b 038b LAR AR3,* ,AR3
311 002c b955 LACK 85
312 002d 908a SACL * ,AR2
313 .line 16
314 ;>>>> Temp1 = (uint *)(BaseAddr+0x5555); //address 5555h
315 002e ae80 SPLK #54613,*
002f d555
316 .line 17
317 ;>>>> *Temp1= 0x90; // write 0x9090
318 0030 038b LAR AR3,* ,AR3
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Thu Dec 8 11:06:36 2005
Copyright (c) 1987-1999 Texas Instruments Incorporated
39vf400.asm PAGE 7
319 0031 b990 LACK 144
320 0032 9089 SACL * ,AR1
321 .line 19
322 ;>>>> Delay_150_Nano_Seconds(); //delay Tida
323 0033 7a80 CALL _Delay_150_Nano_Seconds
0034 0000'
324 .line 21
325 ;>>>> Temp = (uint *)(BaseAddr+0x0000); //address 0000h
326 0035 8b8a MAR * ,AR2
327 0036 b201 LARK AR2,1
328 0037 8be0 MAR *0+
329 0038 ae80 SPLK #32768,*
0039 8000
330 .line 22
331 ;>>>> SST_id1 = *Temp; // get first ID word
332 003a 038b LAR AR3,* ,AR3
333 003b 108a LAC * ,AR2
334 003c 7802 ADRK 2
335 003d 9090 SACL *-
336 .line 23
337 ;>>>> Temp1 = (uint *)(BaseAddr+0x0001); //address 0001h
338 003e ae80 SPLK #32769,*
003f 8001
339 .line 24
340 ;>>>> SST_id2 = *Temp1; // get second ID word
341 0040 048c LAR AR4,* ,AR4
342 0041 108a LAC * ,AR2
343 0042 7802 ADRK 2
344 0043 9090 SACL *-
345 .line 26
346 ;>>>> if ( ((SST_id1&0xff) == SST_ID) && (SST_id2 ==SST_39VF400A))ReturnStatus = TRUE;
347 0044 b9ff LACK 255
348 0045 6e80 AND *
349 0046 babf SUBK 191
350 0047 e308 BNZ L1
0048 0054'
351 0049 8ba0 MAR *+
352 004a 1080 LAC *
353 004b bfa0 SUBK 10112
004c 2780
354 004d e308 BNZ L1
004e 0054'
355 004f b901 LACK 1
356 0050 8ba0 MAR *+
357 0051 9080 SACL *
358 0052 7980 B L2
0053 0058'
359 0054 L1:
360 .line 27
361 ;>>>> else ReturnStatus = FALSE;
362 0054 b900 LACK 0
363 0055 b205 LARK AR2,5
364 0056 8be0 MAR *0+
365 0057 9080 SACL *
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Thu Dec 8 11:06:36 2005
Copyright (c) 1987-1999 Texas Instruments Incorporated
39vf400.asm PAGE 8
366 0058 L2:
367 .line 29
368 ;>>>> Temp1 = (uint *)(BaseAddr+0x5555); //address 5555h
369 0058 7c03 SBRK 3
370 0059 ae80 SPLK #54613,*
005a d555
371 .line 30
372 ;>>>> *Temp1 = 0xAAAA; // 0xAAAA
373 005b 048c LAR AR4,* ,AR4
374 005c ae8a SPLK #43690,* ,AR2
005d aaaa
375 .line 31
376 ;>>>> Temp1 = (uint *)(BaseAddr+0x2AAA); //address 2AAAh
377 005e ae80 SPLK #43690,*
005f aaaa
378 .line 32
379 ;>>>> *Temp1 = 0x5555; //0x5555
380 0060 048c LAR AR4,* ,AR4
381 0061 ae8a SPLK #21845,* ,AR2
0062 5555
382 .line 33
383 ;>>>> Temp1 = (uint *)(BaseAddr+0x5555); //address 5555h
384 0063 ae80 SPLK #54613,*
0064 d555
385 .line 34
386 ;>>>> *Temp1 = 0xF0F0; //0xF0F0
387 0065 048c LAR AR4,* ,AR4
388 0066 ae89 SPLK #61680,* ,AR1
0067 f0f0
389 .line 36
390 ;>>>> Delay_150_Nano_Seconds(); //delay Tida
391 0068 7a80 CALL _Delay_150_Nano_Seconds
0069 0000'
392 .line 37
393 ;>>>> cs_flash_1;
394 006a bf80 LACK 64511
006b fbff
395 006c bc00! LDPK _MCRC
396 006d 6e00! AND _MCRC
397 006e 9000! SACL _MCRC
398 006f bf80 LACK 1028
0070 0404
399 0071 bc00! LDPK _PFDATDIR
400 0072 6d00! OR _PFDATDIR
401 0073 9000! SACL _PFDATDIR
402 .line 38
403 ;>>>> return(ReturnStatus);
404 0074 8b8a MAR * ,AR2
405 0075 b205 LARK AR2,5
406 0076 8be0 MAR *0+
407 0077 6980 ZALS *
408 0078 EPI0_2:
409 .line 39
410 0078 8b89 MAR * ,AR1
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Thu Dec 8 11:06:36 2005
Copyright (c) 1987-1999 Texas Instruments Incorporated
39vf400.asm PAGE 9
411 0079 7c07 SBRK 7
412 007a 0090 LAR AR0,*-
413 007b 7680 PSHD *
414 007c ef00 RET
415
416 .endfunc 87,000000000H,6
417
418 .sym _Erase_One_Sector,_Erase_One_Sector,46,2,0
419 .globl _Erase_One_Sector
420
421 .func 118
422 ;>>>> uint Erase_One_Sector (uint *Dst)
423 ******************************************************
424 * FUNCTION DEF : _Erase_One_Sector
425 ******************************************************
426 007d _Erase_One_Sector:
427
428 0000 LF3 .set 0
429
430 007d 8aa0 POPD *+
431 007e 80a0 SAR AR0,*+
432 007f 8180 SAR AR1,*
433 0080 b003 LARK AR0,3
434 0081 00ea LAR AR0,*0+,AR2
435
436 .sym _Dst,-3+LF3,30,9,16
437 .sym _Temp,1,30,1,16
438 .sym _flag,2,14,1,16
439 .line 2
440 ;>>>> uint *Temp;
441 .line 4
442 ;>>>> uint flag = 1;
443 0082 b901 LACK 1
444 0083 b202 LARK AR2,2
445 0084 8be0 MAR *0+
446 0085 9090 SACL *-
447 .line 6
448 ;>>>> cs_flash_0;
449 0086 bf80 LACK 64511
0087 fbff
450 0088 bc00! LDPK _MCRC
451 0089 6e00! AND _MCRC
452 008a 9000! SACL _MCRC
453 008b bf80 LACK 1024
008c 0400
454 008d bc00! LDPK _PFDATDIR
455 008e 6d00! OR _PFDATDIR
456 008f 9000! SACL _PFDATDIR
457 0090 bf80 LACK 65531
0091 fffb
458 0092 6e00! AND _PFDATDIR
459 0093 9000! SACL _PFDATDIR
460 .line 8
461 ;>>>> Temp = (uint *)(BaseAddr+0x5555); // set up address to be C000:5555h
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Thu Dec 8 11:06:36 2005
Copyright (c) 1987-1999 Texas Instruments Incorporated
39vf400.asm PAGE 10
462 0094 ae80 SPLK #54613,*
0095 d555
463 .line 9
464 ;>>>> *Temp = 0xAAAA; // write data 0xAAAA to the address
465 0096 038b LAR AR3,* ,AR3
466 0097 ae8a SPLK #43690,* ,AR2
0098 aaaa
467 .line 11
468 ;>>>> Temp = (uint *)(BaseAddr+0x2AAA); // set up address to be C000:2AAAh
469 0099 ae80 SPLK #43690,*
009a aaaa
470 .line 12
471 ;>>>> *Temp = 0x5555; // write data 0x5555 to the address
472 009b 038b LAR AR3,* ,AR3
473 009c ae8a SPLK #21845,* ,AR2
009d 5555
474 .line 14
475 ;>>>> Temp = (uint *)(BaseAddr+0x5555); // set up address to be C000:5555h
476 009e ae80 SPLK #54613,*
009f d555
477 .line 15
478 ;>>>> *Temp = 0x8080; // write data 0x8080 to the address
479 00a0 038b LAR AR3,* ,AR3
480 00a1 ae8a SPLK #32896,* ,AR2
00a2 8080
481 .line 17
482 ;>>>> Temp = (uint *)(BaseAddr+0x5555); // set up address to be C000:5555h
483 00a3 ae80 SPLK #54613,*
00a4 d555
484 .line 18
485 ;>>>> *Temp = 0xAAAA; // write data 0xAAAA to the address
486 00a5 038b LAR AR3,* ,AR3
487 00a6 ae8a SPLK #43690,* ,AR2
00a7 aaaa
488 .line 20
489 ;>>>> Temp = (uint *)(BaseAddr+0x2AAA); // set up address to be C000:2AAAh
490 00a8 ae80 SPLK #43690,*
00a9 aaaa
491 .line 21
492 ;>>>> *Temp = 0x5555; // write data 0x5555 to the address
493 00aa 038b LAR AR3,* ,AR3
494 00ab ae8a SPLK #21845,* ,AR2
00ac 5555
495 .line 23
496 ;>>>> Temp = Dst; // set up starting address to be erased
497 00ad 7c04 SBRK 4-LF3
498 00ae 1080 LAC *
499 00af 7804 ADRK 4-LF3
500 00b0 9080 SACL *
501 .line 24
502 ;>>>> *Temp = 0x3030; // write data 0x3030 to the address
503 00b1 038b LAR AR3,* ,AR3
504 00b2 ae89 SPLK #12336,* ,AR1
00b3 3030
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Thu Dec 8 11:06:36 2005
Copyright (c) 1987-1999 Texas Instruments Incorporated
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