rt2570.h

台湾RALink公司的 rt2570无线 802.11g 网卡的 驱动的源代码 ,支持linux2.4以上的 内河

/*
 ***************************************************************************
 * Ralink Tech Inc.
 * 4F, No. 2 Technology 5th Rd.
 * Science-based Industrial Park
 * Hsin-chu, Taiwan, R.O.C.
 *
 * (c) Copyright 2002-2004, Ralink Technology, Inc.
 *
 * This program is free software; you can redistribute it and/or modify  * 
 * it under the terms of the GNU General Public License as published by  * 
 * the Free Software Foundation; either version 2 of the License, or     * 
 * (at your option) any later version.                                   * 
 *                                                                       * 
 * This program is distributed in the hope that it will be useful,       * 
 * but WITHOUT ANY WARRANTY; without even the implied warranty of        * 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         * 
 * GNU General Public License for more details.                          * 
 *                                                                       * 
 * You should have received a copy of the GNU General Public License     * 
 * along with this program; if not, write to the                         * 
 * Free Software Foundation, Inc.,                                       * 
 * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             * 
 *                                                                       * 
 ************************************************************************
	Module Name:
	rt2570.h

	Abstract:

	Revision History:
	Who			When			What
	--------	----------		----------------------------------------------
	Name		Date			Modification logs
	Jan Lee		2005-06-01		Release
*/

#ifndef	__RT2570_H__
#define	__RT2570_H__

//
// Control/Status Registers	(CSR)
//
#define	MAC_CSR0		0x00	// ASIC	version
#define	MAC_CSR1		0x02	// system control
#define	MAC_CSR2		0x04	// MAC addr0
#define	MAC_CSR3		0x06	// MAC addr1
#define	MAC_CSR4		0x08	// MAC addr2
#define	MAC_CSR5		0x0A	// BSSID0
#define	MAC_CSR6		0x0C	// BSSID1
#define	MAC_CSR7		0x0E	// BSSID2
#define	MAC_CSR8		0x10	// max frame length
#define	MAC_CSR9		0x12	// timer control
#define	MAC_CSR10		0x14	// slot time
#define	MAC_CSR11		0x16	// IFS
#define	MAC_CSR12		0x18	// EIFS
#define	MAC_CSR13		0x1A	// power mode0
#define	MAC_CSR14		0x1C	// power mode1
#define	MAC_CSR15		0x1E	// power saving transition0
#define	MAC_CSR16		0x20	// power saving transition1
#define	MAC_CSR17		0x22	// power state control
#define	MAC_CSR18		0x24	// auto wake-up control
#define	MAC_CSR19		0x26	// GPIO control
#define	MAC_CSR20		0x28	// LED control0
#define	MAC_CSR21		0x2A	// LED control1
#define	MAC_CSR22		0x2C	// LED control1

#define	TXRX_CSR0		0x40		// security control
#define	TXRX_CSR1		0x42		// TX configuration
#define	TXRX_CSR2		0x44		// RX control
#define	TXRX_CSR3		0x46		// CCK RX BBP ID
#define	TXRX_CSR4		0x48		// OFDM RX BBP ID
#define	TXRX_CSR5		0x4A		// CCK TX BBP ID0
#define	TXRX_CSR6		0x4C		// CCK TX BBP ID1
#define	TXRX_CSR7		0x4E		// OFDM TX BBP ID0
#define	TXRX_CSR8		0x50		// OFDM TX BBP ID1
#define	TXRX_CSR9		0x52		// TX ACK time-out
#define	TXRX_CSR10		0x54		// auto responder control
#define	TXRX_CSR11		0x56		// auto responder basic rate
#define	TXRX_CSR12		0x58		// ACK/CTS time0
#define	TXRX_CSR13		0x5A		// ACK/CTS time1
#define	TXRX_CSR14		0x5C		// ACK/CTS time2
#define	TXRX_CSR15		0x5E		// ACK/CTS time3
#define	TXRX_CSR16		0x60		// ACK/CTS time4
#define	TXRX_CSR17		0x62		// ACK/CTS time5
#define	TXRX_CSR18		0x64		// Beacon interval
#define	TXRX_CSR19		0x66		// Beacon/sync control
#define	TXRX_CSR20		0x68		// Beacon alignment
#define	TXRX_CSR21		0x6A		// blue

//WEP key registers
#define	SEC_CSR0		0x80	// shared key 0, word 0
#define	SEC_CSR1		0x82	// shared key 0, word 1
#define	SEC_CSR2		0x84	// shared key 0, word 2
#define	SEC_CSR3		0x86	// shared key 0, word 3
#define	SEC_CSR4		0x88	// shared key 0, word 4
#define	SEC_CSR5		0x8A	// shared key 0, word 5
#define	SEC_CSR6		0x8C	// shared key 0, word 6
#define	SEC_CSR7		0x8E	// shared key 0, word 7
#define	SEC_CSR8		0x90	// shared key 1, word 0
#define	SEC_CSR9		0x92	// shared key 1, word 1
#define	SEC_CSR10		0x94	// shared key 1, word 2
#define	SEC_CSR11		0x96	// shared key 1, word 3
#define	SEC_CSR12		0x98	// shared key 1, word 4
#define	SEC_CSR13		0x9A	// shared key 1, word 5
#define	SEC_CSR14		0x9C	// shared key 1, word 6
#define	SEC_CSR15		0x9E	// shared key 1, word 7
#define	SEC_CSR16		0xA0	// shared key 2, word 0
#define	SEC_CSR17		0xA2	// shared key 2, word 1
#define	SEC_CSR18		0xA4	// shared key 2, word 2
#define	SEC_CSR19		0xA6	// shared key 2, word 3
#define	SEC_CSR20		0xA8	// shared key 2, word 4
#define	SEC_CSR21		0xAA	// shared key 2, word 5
#define	SEC_CSR22		0xAC	// shared key 2, word 6
#define	SEC_CSR23		0xAE	// shared key 2, word 7
#define	SEC_CSR24		0xB0	// shared key 3, word 0
#define	SEC_CSR25		0xB2	// shared key 3, word 1
#define	SEC_CSR26		0xB4	// shared key 3, word 2
#define	SEC_CSR27		0xB6	// shared key 3, word 3
#define	SEC_CSR28		0xB8	// shared key 3, word 4
#define	SEC_CSR29		0xBA	// shared key 3, word 5
#define	SEC_CSR30		0xBC	// shared key 3, word 6
#define	SEC_CSR31		0xBE	// shared key 3, word 7

//PHY control registers
#define	PHY_CSR0		0xC0	// RF switching timing control
#define	PHY_CSR1		0xC2	// TX PA configuration
#define	PHY_CSR2		0xC4	// TX MAC configuration
#define	PHY_CSR3		0xC6	// RX MAC configuration
#define	PHY_CSR4		0xC8	// interface configuration
#define	PHY_CSR5		0xCA	// BBP pre-TX CCK
#define	PHY_CSR6		0xCC	// BBP pre-TX OFDM
#define	PHY_CSR7		0xCE	// BBP serial control
#define	PHY_CSR8		0xD0	// BBP serial status
#define	PHY_CSR9		0xD2	// RF serial control0
#define	PHY_CSR10		0xD4	// RF serial control1


// Statistic Register
#define	STA_CSR0		0xE0		// FCS error
#define	STA_CSR1		0xE2		// PLCP error
#define	STA_CSR2		0xE4		// LONG error
#define	STA_CSR3		0xE6		// CCA false alarm
#define	STA_CSR4		0xE8		// RX FIFO overflow
#define	STA_CSR5		0xEA		// Beacon sent counter
#define	STA_CSR6		0xEC
#define	STA_CSR7		0xEE
#define	STA_CSR8		0xF0
#define	STA_CSR9		0xF2
#define	STA_CSR10		0xF4

//
// BBP & RF	definition
//
#define	BUSY		1
#define	IDLE		0

#define	BBP_Version					0x00
#define	BBP_Tx_Configure			2  // R2
#define	BBP_Tx_Tssi					1  // R1,blue
#define	BBP_Rx_Configure			14 // R14

#define PHY_TR_SWITCH_TIME          5  // usec

#define BBP_R17_LOW_SENSIBILITY     0x48
#define BBP_R17_MID_SENSIBILITY     0x41
#define BBP_R17_DYNAMIC_UP_BOUND    0x40
#define RSSI_FOR_LOW_SENSIBILITY    -58
#define RSSI_FOR_MID_SENSIBILITY    -74
//#define RSSI_HIGH_WATERMARK         -53
//#define RSSI_LOW_WATERMARK          -58

//-------------------------------------------------------------------------
// EEPROM definition
//-------------------------------------------------------------------------
#define EEDO        0x10
#define EEDI        0x08
#define EECS        0x04
#define EESK        0x02
#define EERL        0x01

#define EEPROM_WRITE_OPCODE     0x05
#define EEPROM_READ_OPCODE      0x06
#define EEPROM_EWDS_OPCODE      0x10
#define EEPROM_EWEN_OPCODE      0x13



#define	NUM_EEPROM_BBP_PARMS		19
#define	NUM_EEPROM_TX_PARMS			7
#define	NUM_EEPROM_BBP_TUNING_PARMS	7
#define EEPROM_VERSION_OFFSET       0x2
#define	EEPROM_MAC_ADDRESS_BASE_OFFSET		0x4
#define	EEPROM_BBP_BASE_OFFSET		0x16
#define	EEPROM_TX_PWR_OFFSET		0x3C
#define	EEPROM_TSSI_REF_OFFSET		0x4A
#define	EEPROM_TSSI_DELTA_OFFSET	0x1A
#define	EEPROM_BBP_TUNING_OFFSET	0x60
#define	EEPROM_MAC_STATUS_OFFSET	0x7E


// =================================================================================
// TX / RX ring descriptor format
// =================================================================================

//
// TX descriptor format
//
typedef	struct	_TXD_STRUC
{
	// Word    0
	ULONG				PacketID:4;// PacketID - write by MAC about Frame translate status
	ULONG				RetryLimit:4;// Retry limit
	ULONG				MoreFrag:1;// More     fragment following this       tx ring
	ULONG				ACK:1;// ACK
	ULONG				Timestamp:1;// ins_TSF
	ULONG				Ofdm:1;// OFDM
	ULONG				newseq:1;// new_seq
	ULONG				IFS:2;// IFS
	ULONG				Rsv0:1;// Rev0
	
	ULONG				DataByteCnt:12;// Data byte count
	ULONG				Rsv1:1;// Rev1
	ULONG				Cipher:1;// cliper
	ULONG				KeyID:2;// KeyID
	
	
	
	// Word    1
	ULONG				IvOffset:6;// IV offset
	ULONG				Aifs:2;// AIFS
	ULONG				CWmin:4;// CWmin
	ULONG				CWmax:4;// CWmax
	ULONG				Rsv2:16;// Rev2
	
	
	
	// Word    2
	ULONG				PlcpSignal:8;// BBP R0 - PLCP Singal
	ULONG				PlcpService:8;// BBP R1 - PLCP Service
	ULONG				PlcpLengthLow:8;// BBP R2 - PLCP length_Low
	ULONG				PlcpLengthHigh:8;// BBP R3 - PLCP length_high
	
	
	
	// Word    3
	ULONG				Iv;// IV
	
	
	
	// Word    4
	ULONG				Eiv;// EIV
}
TXD_STRUC, *PTXD_STRUC;

//
// Rx descriptor format
//
typedef	struct	_RXD_STRUC
{
	// Word    0
	ULONG				Rev0:1;// Rev0
	ULONG				U2M:1;// u2me
	ULONG				Mcast:1;// mcast
	ULONG				Bcast:1;// bcast
	ULONG				MyBss:1;// my bss
	ULONG				Crc:1;// crc error
	ULONG				Ofdm:1;// OFDM
	ULONG				PhyErr:1;// phy err
	ULONG				Cipher:1;// cipher
	ULONG				CiErr:1;// ci error
	ULONG				Rsv1:6;// Rev1
	
	ULONG				DataByteCnt:12;// data byte count
	ULONG				Rsv2:4;// Rev2
	
	
	
	// Word    1
	UCHAR				BBR1;// BBP R0 - SIGNAL / rate
	UCHAR				BBR0;// BBP R1 - RSSI
	UCHAR				Rev3[2];// Rev3
	
	
	
	// Word    2
	ULONG				Iv;// IV
	
	
	
	// Word 3
	ULONG				Eiv;// EIV
}
RXD_STRUC, *PRXD_STRUC;


// =================================================================================
// CSR Registers
// =================================================================================

//
// CSR1: System control register
//
typedef	union	_CSR1_STRUC	{
	struct	{
		ULONG		SoftReset:1;		// Software reset bit, 1: reset, 0: normal
		ULONG		Rsvd0:1;
		ULONG		HostReady:1;		// Host is ready after initialization, 1: ready
		ULONG		Rsvd1:29;
	}	field;
	ULONG			word;
}	CSR1_STRUC, *PCSR1_STRUC;

// MAC_CSR2: STA MAC register 0
typedef	union	_MAC_CSR2_STRUC	{
	struct	{
		UCHAR		Byte0;		// MAC address byte 0
		UCHAR		Byte1;		// MAC address byte 1
	}				field;
	USHORT			value;
}	MAC_CSR2_STRUC, *PMAC_CSR2_STRUC;

// MAC_CSR3: STA MAC register 1
typedef	union	_MAC_CSR3_STRUC	{
	struct	{
		UCHAR		Byte2;		// MAC address byte 2
		UCHAR		Byte3;		// MAC address byte 3
	}				field;
	USHORT			value;
}	MAC_CSR3_STRUC, *PMAC_CSR3_STRUC;

// MAC_CSR4: STA MAC register 2
typedef	union	_MAC_CSR4_STRUC	{
	struct	{
		UCHAR		Byte4;		// MAC address byte 4
		UCHAR		Byte5;		// MAC address byte 5
	}				field;
	USHORT			value;
}	MAC_CSR4_STRUC, *PMAC_CSR4_STRUC;
#if 0//rt2460
//
// CSR3: STA MAC register 0
//
typedef	union	_CSR3_STRUC	{
	struct	{
		UCHAR		Byte0;		// MAC address byte 0
		UCHAR		Byte1;		// MAC address byte 1
		UCHAR		Byte2;		// MAC address byte 2
		UCHAR		Byte3;		// MAC address byte 3
	}	field;
	ULONG			word;
}	CSR3_STRUC, *PCSR3_STRUC;

//
// CSR4: STA MAC register 1