my_ez80f91.h

ucos_ii 在Z80系列单片机上的移植

/************************************************************/
/*                                                          */
/* my_eZ80F91.h -- my eZ80F91 Internal I/O Port Definitions */
/*          ( because ZiLOG's are a nightmare )             */
/*                                                          */
/*  Copyright (C) 2004, Douglas Beattie Jr.                 */
/*                                                          */
/************************************************************/

#ifndef _MY_EZ80F91_H_
#define _MY_EZ80F91_H_

typedef volatile unsigned char __INTIO *PBINTIO;
typedef volatile unsigned char __EXTIO *PBEXTIO;


/* -- Programmable Reload Counter/Timers */
/* -- example usage: x=TMRx_RR_L(TMR2);  */

#define TMR0 0x80
#define TMR1 0x83
#define TMR2 0x86
#define TMR3 0x89
#define TMR4 0x8C
#define TMR5 0x8F

#define TMRx_CTL(FNbase) ((PBINTIO) (FNbase+0))[0]   /* Timer Control Register */
#define TMRx_IIR(FNbase) ((PBINTIO) (FNbase+1))[0]   /* Timer INT ID Register */
#define TMRx_IER(FNbase) ((PBINTIO) (FNbase+2))[0]   /* Timer INT Enable Register */
#define TMRx_DR_L(FNbase) ((PBINTIO) (FNbase+3))[0]  /* Timer Data Register, Low Byte */
#define TMRx_RR_L(FNbase) ((PBINTIO) (FNbase+3))[0]  /* Timer Reload Register, Low Byte */
#define TMRx_DR_H(FNbase) ((PBINTIO) (FNbase+4))[0]  /* Timer Data Register, High Byte */
#define TMRx_RR_H(FNbase) ((PBINTIO) (FNbase+4))[0]  /* Timer Reload Register, High Byte */
//#define TMR_ISS     (*(PBINTIO)0x92)

/* -- Watch-Dog Timer */

#define WDT_CTL (*(PBINTIO)0x93)    /* Watch-Dog Timer Control Register */
#define WDT_RR  (*(PBINTIO)0x94)     /* Watch-Dog Timer Reset Register */

/* -- General-Purpose Input/Output Ports */

#define PortA 0x96
#define PortB 0x9A
#define PortC 0x9E
#define PortD 0xA2

#define Px_DR(FNbase) ((PBINTIO) (FNbase+0))[0]    /* Port Data Register */
#define Px_DDR(FNbase) ((PBINTIO) (FNbase+1))[0]   /* Port Data Direction Register */
#define Px_ALT1(FNbase) ((PBINTIO) (FNbase+2))[0]  /* Port Alternate Register 1 */
#define Px_ALT2(FNbase) ((PBINTIO) (FNbase+3))[0]  /* Port Alternate Register 2 */


/* --Chip Select/Wait State Generator    */
/* -- example usage: CSx_LBR(CS2)=x;     */

#define CS0 0xA8
#define CS1 0xAB
#define CS2 0xAE
#define CS3 0xB1

#define CSx_LBR(FNbase) ((PBINTIO) (FNbase+0))[0]  /* Chip Select Lower Bound Register */
#define CSx_UBR(FNbase) ((PBINTIO) (FNbase+1))[0]  /* Chip Select Upper Bound Register */
#define CSx_CTL(FNbase) ((PBINTIO) (FNbase+2))[0]  /* Chip Select Control Register */

/* -- On-Chip RAM Control */

#define RAM_CTL    (*(PBINTIO)0xB4)  /* RAM Control Register */
#define RAM_ADDR_U (*(PBINTIO)0xB5)  /* RAM Address Upper Byte */
#define MBIST_GPR   (*(PBINTIO)0xB6)
#define MBIST_EMR   (*(PBINTIO)0xB7)
#define RAM_CTL0 RAM_CTL

/* --Universal ZiLOG Interface Blocks */

#define SPI_BRG_L (*(PBINTIO)0xB8)    /*SPI Baud Rate Generator Low Byte */
#define SPI_BRG_H (*(PBINTIO)0xB9)    /*SPI Baud Rate Generator Low Byte */
#define SPI_CTL   (*(PBINTIO)0xBA)    /* SPI Control Register */
#define SPI_SR    (*(PBINTIO)0xBB)    /* SPI Status Register */
#define SPI_RBR   (*(PBINTIO)0xBC)    /* SPI Receive Buffer Register */
#define SPI_TSR   (*(PBINTIO)0xBD)    /* SPI Transmit Shift Register */


/* -- UART Registers                     */
/* -- example usage: UART_THR(UART1)=x;  */

#define UART0 0xC0
#define UART1 0xD0

#define UART_RBR(FNbase) ((PBINTIO) (FNbase+0))[0]   /*  UART Receive Buffer Register */
#define UART_THR(FNbase) ((PBINTIO) (FNbase+0))[0]   /*  UART Transmit Holding Register */
#define BRG_DLR_L(FNbase) ((PBINTIO) (FNbase+0))[0]  /*  BRG Divisor Latch Register, Low Byte */
#define BRG_DLR_H(FNbase) ((PBINTIO) (FNbase+1))[0]  /*  BRG Divisor Latch Register, High Byte */
#define UART_IER(FNbase) ((PBINTIO) (FNbase+1))[0]   /*  UART Interrupt Enable Register */
#define UART_IIR(FNbase) ((PBINTIO) (FNbase+2))[0]   /*  UART Interrupt Identification Register */
#define UART_FCTL(FNbase) ((PBINTIO) (FNbase+2))[0]  /*  UART FIFO Control Register */
#define UART_LCTL(FNbase) ((PBINTIO) (FNbase+3))[0]  /*  UART Line Control Register */
#define UART_MCTL(FNbase) ((PBINTIO) (FNbase+4))[0]  /*  UART Modem Control Register */
#define UART_LSR(FNbase) ((PBINTIO) (FNbase+5))[0]   /*  UART Line Status Register */
#define UART_MSR(FNbase) ((PBINTIO) (FNbase+6))[0]   /*  UART Modem Status Register */
#define UART_SPR(FNbase) ((PBINTIO) (FNbase+7))[0]   /*  UART Scratch Pad Register */


#define I2C_SAR   (*(PBINTIO)0xC8)    /* I2C Slave Address Register */
#define I2C_XSAR  (*(PBINTIO)0xC9)    /* I2C Extended Slave Address Register */
#define I2C_DR    (*(PBINTIO)0xCA)    /* I2C Data Register */
#define I2C_CTL   (*(PBINTIO)0xCB)    /* I2C Control Register */
#define I2C_SR    (*(PBINTIO)0xCC)    /* I2C Status Register */
#define I2C_CCR   (*(PBINTIO)0xCC)    /* I2C Clock Control Register */
#define I2C_SRR   (*(PBINTIO)0xCD)    /* I2C Software Reset Register */

#define CLK_PPD1  (*(PBINTIO)0xDB)    /* */
#define CLK_PPD2  (*(PBINTIO)0xDC)    /* */

/* -- Real-Time Clock (RTC) Registers    */


#define RTC_SEC   (*(PBINTIO)0xE0)     /* RTC Seconds */
#define RTC_MIN   (*(PBINTIO)0xE1)     /* */
#define RTC_HRS   (*(PBINTIO)0xE2)     /* */
#define RTC_DOW   (*(PBINTIO)0xE3)     /* RTC Day of Week */
#define RTC_DOM   (*(PBINTIO)0xE4)     /* RTC Date of Month*/
#define RTC_MON   (*(PBINTIO)0xE5)     /* RTC Month */
#define RTC_YR    (*(PBINTIO)0xE6)     /* RTC Year */
#define RTC_CEN   (*(PBINTIO)0xE7)     /* RTC Century */
#define RTC_ASEC  (*(PBINTIO)0xE8)     /* Alarm Seconds */
#define RTC_AMIN  (*(PBINTIO)0xE9)     /* */
#define RTC_AHRS  (*(PBINTIO)0xEA)     /* */
#define RTC_ADOW  (*(PBINTIO)0xEB)     /* */
#define RTC_ACTRL (*(PBINTIO)0xEC)     /* Alarm Control */
#define RTC_CTRL  (*(PBINTIO)0xED)     /* */

/* Chip-Select Bus Mode Control Registers */

#define CS0_BMC   (*(PBINTIO)0xF0)     /* */
#define CS1_BMC   (*(PBINTIO)0xF1)     /* */
#define CS2_BMC   (*(PBINTIO)0xF2)     /* */
#define CS3_BMC   (*(PBINTIO)0xF3)     /* */

/* Flash Memory Controller                 */

#define FLASH_KEY    (*(PBINTIO)0xF5)     /* */
#define FLASH_DATA   (*(PBINTIO)0xF6)     /* */
#define FLASH_ADDR_U (*(PBINTIO)0xF7)     /* */
#define FLASH_CTRL   (*(PBINTIO)0xF8)     /* */
#define FLASH_FDIV   (*(PBINTIO)0xF9)     /* */
#define FLASH_PROT   (*(PBINTIO)0xFA)     /* */
#define FLASH_IRQ    (*(PBINTIO)0xFB)     /* */
#define FLASH_PAGE   (*(PBINTIO)0xFC)     /* */
#define FLASH_ROW    (*(PBINTIO)0xFD)     /* */
#define FLASH_COL    (*(PBINTIO)0xFE)     /* */
#define FLASH_PGCTL  (*(PBINTIO)0xFF)     /* */

#endif /* _EZ80F92_H_ */