rhine.h

联想网卡驱动 linux环境下编写 初写驱动的同志参考以下

	struct sk_buff*		skb;
	PU8					buf;
	dma_addr_t			skb_dma;
	dma_addr_t			buf_dma;
	dma_addr_t			curr_desc;
} RHINE_TD_INFO,	*PRHINE_TD_INFO;

static inline PRHINE_TD_INFO alloc_td_info(void) {
	PRHINE_TD_INFO	ptr;
	if ((ptr=kmalloc(sizeof(RHINE_TD_INFO),GFP_ATOMIC))==NULL)
		return NULL;
	else {
		memset(ptr,0,sizeof(RHINE_TD_INFO));
		return ptr;
	}
}

typedef struct _tx_desc {
	volatile TDESC0				tdesc0;
	volatile TDESC1				tdesc1;
	volatile U32				buff_addr;
	volatile U32				next_desc;
	struct _tx_desc* 			next;		//4 bytes
	PRHINE_TD_INFO				pInfo;		//4 bytes
	volatile U32				Reserved[2];//8 bytes
} __attribute__ ((__packed__)) 
TX_DESC, *PTX_DESC;

typedef enum _speed_opt {
	SPD_DPX_AUTO=0,
	SPD_DPX_100_HALF=1,
	SPD_DPX_100_FULL=2,
	SPD_DPX_10_HALF=3,
	SPD_DPX_10_FULL=4
} SPD_DPX_OPT, *PSPD_DPX_OPT;

//flags for options
#define		RHINE_FLAGS_TAGGING			0x00000001UL
#define		RHINE_FLAGS_TX_CSUM			0x00000002UL
#define		RHINE_FLAGS_RX_CSUM			0x00000004UL
#define		RHINE_FLAGS_IP_ALIGN		0x00000008UL
#define		RHINE_FLAGS_VAL_PKT_LEN		0x00000010UL

//flags for driver status
#define		RHINE_FLAGS_OPENED			0x00010000UL
#define		RHINE_FLAGS_VMNS_CONNECTED	0x00020000UL
#define		RHINE_FLAGS_VMNS_COMMITTED	0x00040000UL

//flags for capbilities
#define		RHINE_FLAGS_TX_ALIGN		0x01000000UL
#define		RHINE_FLAGS_HAVE_CAM		0x02000000UL
#define 	RHINE_FLAGS_FLOW_CTRL		0x04000000UL

//flags for MII status
#define 	RHINE_LINK_FAIL				0x00000001UL
#define		RHINE_SPEED_10				0x00000002UL
#define		RHINE_SPEED_100				0x00000004UL
#define		RHINE_SPEED_1000			0x00000008UL
#define		RHINE_DUPLEX_FULL			0x00000010UL
#define		RHINE_AUTONEG_ENABLE		0x00000020UL
#define		RHINE_FORCED_BY_EEPROM		0x00000040UL


typedef struct __rhine_opt {
	int			nRxDescs;		//Number of RX descriptors
	int			nTxDescs;		//Number of TX descriptors
	SPD_DPX_OPT	spd_dpx;		//Media link mode
	int			vid;            //vlan id
	int			tx_thresh;      //Tx Fifo threshold
	int			rx_thresh;		//Rx fifo threshold
	int			DMA_length;     //DMA length
	int			flow_cntl;
	U32			flags;
} OPTIONS, *POPTIONS;

typedef struct __mac_regs {
    volatile U8    abyPAR[6];                  // 0x00
    volatile U8    byRCR;
    volatile U8    byTCR;

    volatile U8    byCR0;                      // 0x08
    volatile U8    byCR1;
    volatile U8    byTXQWAK;
    volatile U8    wReserve0B;

    volatile U8    byISR0;                     // 0x0C
    volatile U8    byISR1;
    volatile U8    byIMR0;
    volatile U8    byIMR1;

    volatile U8    abyMAR[8];                  // 0x10

    volatile U32   dwCurrRxDescAddr;           // 0x18
    volatile U32   adwCurrTxDescAddr[8];

    volatile U32   dwCurrentRDSE0;             // 0x3C
    volatile U32   dwCurrentRDSE1;
    volatile U32   dwCurrentRDSE2;
    volatile U32   dwCurrentRDSE3;
    volatile U32   dwCurrentTDSE0;             // 0x4C
    volatile U32   dwCurrentTDSE1;
    volatile U8    byGFTEST;
    volatile U8    byRFTCMD;
    volatile U8    byTFTCMD;
    volatile U8    byCFSTATUS;					// 0x57
    volatile U16   wBNRY;						// 0x58
    volatile U16   wCURR;						// 0x5a
    volatile U32   dwFIFODataPort;				// 0x5c
    volatile U32   dwCurrentTDSE2;				// 0x60
    volatile U32   dwCurrentTDSE3;				// 0x64
	volatile U32   dwReserverd_68;

    volatile U8    byMIICFG;					// 0x6C
    volatile U8    byMIISR;
    volatile U8    byBCR0;
    volatile U8    byBCR1;
    volatile U8    byMIICR;
    volatile U8    byMIIAD;
    volatile U16   wMIIDATA;

    volatile U8    byEECSR;						// 0x74
    volatile U8    byTEST;
    volatile U8    byDEBUG0;
    volatile U8    byDEBUG1;

    volatile U8    byCFGA;                     // 0x78
    volatile U8    byCFGB;
    volatile U8    byCFGC;
    volatile U8    byCFGD;

    // tally counter will be reset when read each time
    volatile U16   wReserved_7C;               // 0x7C
    volatile U16   wReserved_7E;

    // for VT6102
    volatile U8    byMISCCR0;                  // 0x80
    volatile U8    byMISCCR1;
    volatile U8    byPMCPORT;
    volatile U8    bySTICKHW;
    volatile U8    byMISR;
    volatile U8    byReserved_85;
    volatile U8    byMIMR;
    volatile U8    byReserved_87;
    volatile U32   dwCAMMASK;                  //
    volatile U16   wBPMA;
    volatile U8    byRamBist;
    volatile U8    byBPMD;
    volatile U8    byBPCMD;
    volatile U8    byBPINDATA;
    volatile U8    byCAMCR;
    volatile U8    byCAMADD;
    volatile U8    byMIBCR;
    volatile U8    byPHY_ANR;
    volatile U8    byMIBTestPort;
    volatile U8    byMIBContent;
    volatile U8    byFlowCR0;
    volatile U8    byFlowCR1;
    volatile U16   wTxPasueTimer;
    volatile U16   wSOFTTIMER[2];

    volatile U8    byWOLCRSet;                 // 0xA0
    volatile U8    byPWCFGSet;
    volatile U8    byReserved_A2;
    volatile U8    byWOLCGSet;
    volatile U8    byWOLCRClr;
    volatile U8    byPWCFGClr;
    volatile U8    byReserved_A6;
    volatile U8    byWOLCGClr;
    volatile U8    byPWRCSRSet;
    volatile U8    byReserved_A9[3];
    volatile U8    byPWRCSRClr;
    volatile U8    wReserved_AD[3];
    volatile U32   dwPatternCRC[4];
    volatile U32   adwByteMask[4][4];          // 0xC0
} 
__attribute__ ((__packed__))
MAC_REGS,	*PMAC_REGS;


typedef struct __rhine_info {
	struct __rhine_info*		next;
	struct __rhine_info*		prev;

	struct pci_dev*				pcid;
	struct net_device*			dev;
	struct net_device_stats		stats;
	
	dma_addr_t					pool_dma;
	dma_addr_t					rd_pool_dma;
	dma_addr_t					td_pool_dma[TX_QUEUE_NO];	

	dma_addr_t					tx_bufs_dma;
	PU8							tx_bufs;
			
	CHIP_TYPE					chip_id;
	
	PMAC_REGS					pMacRegs;
	U32							memaddr;
	U32							ioaddr;
	U32							io_size;
	
	U8							byRevId;
	U16							SubSystemID;
	U16							SubVendorID;

#define	AVAIL_TD(p,q)	((p)->sOpts.nTxDescs-((p)->iTDUsed[(q)]))

	int							nTxQueues;
	volatile int				iTDUsed[TX_QUEUE_NO];
	volatile PTX_DESC			apCurrTD[TX_QUEUE_NO];
	volatile PTX_DESC			apTailTD[TX_QUEUE_NO];
	PTX_DESC					apTDRings[TX_QUEUE_NO];

	PRX_DESC					pCurrRD;
	PRX_DESC					aRDRing;

	OPTIONS						sOpts;
		
	U32							IntMask;	

	U32							flags; 
	
	int							rx_buf_sz;
	U32							mii_status;
	int							multicast_limit;
	spinlock_t					lock;
	
#ifdef CONFIG_PROC_FS
	struct proc_dir_entry*		pProcDir;
#endif
	
#ifdef	VMNS
	PVMNS_DRV_PRIVATE			vmns_priv;		
#endif
	
} RHINE_INFO, *PRHINE_INFO;


static inline void rhine_disable_int(PRHINE_INFO pInfo) {
	PMAC_REGS	pMacRegs=pInfo->pMacRegs;
	writew(0, &pMacRegs->byIMR0);
	if (pInfo->byRevId>REV_ID_VT6102_A)
		writeb(0,	&pMacRegs->byMIMR);
}

static inline void rhine_enable_int(PRHINE_INFO pInfo) {
	PMAC_REGS	pMacRegs=pInfo->pMacRegs;
	writew(pInfo->IntMask, &pMacRegs->byIMR0);

	if (pInfo->byRevId>REV_ID_VT6102_A)
		writeb(pInfo->IntMask>>16, &pMacRegs->byMIMR);
}

static inline void enable_mmio(PRHINE_INFO pInfo) {
    int n;
    if (pInfo->chip_id == VT86C100A) {
		n = inb(pInfo->ioaddr + MAC_REG_CFGA) | 0x20;
		outb(n, pInfo->ioaddr + MAC_REG_CFGA);
	} else {
		n = inb(pInfo->ioaddr + MAC_REG_CFGD) | CFGD_GPIOEN;
		outb(n, pInfo->ioaddr + MAC_REG_CFGD);
    }                                                        
}

static inline void	reload_eeprom(PRHINE_INFO pInfo) {
	int i;
	PMAC_REGS	pMacRegs=pInfo->pMacRegs;
	
	writeb(readb(&pMacRegs->byEECSR)|EECSR_AUTOLD, &pMacRegs->byEECSR);
	
	    /* Typically 2 cycles to reload. */
    for (i = 0; i < 150; i++)
    	if (!(readb(&pMacRegs->byEECSR) & EECSR_AUTOLD))
		    break;
	
	enable_mmio(pInfo);
}




static inline void enable_flow_control(PRHINE_INFO pInfo) {
	PMAC_REGS	pMacRegs=pInfo->pMacRegs;

	/* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1} 
		depend on RD=64, and Turn on XNOEN in FlowCR1*/		
	BYTE_REG_BITS_SET(
		(FLOWCR1_XONEN|FLOWCR1_XHITH1|FLOWCR1_XLTH1|FLOWCR1_XLTH0), 
		0xFF,&pMacRegs->byFlowCR1);
		
    /* Set TxPauseTimer to 0xFFFF */    
	writew(0xFFFF, &pMacRegs->wTxPasueTimer);
	
    /* Initialize RBRDU to Rx buffer count.*/	
	writeb(pInfo->sOpts.nRxDescs,&pMacRegs->byFlowCR0);
}
                 
 #define MII_REG_BITS_ON(x,i,p) do {\
	U16	w;\
	rhine_mii_read((p),(i),&(w));\
	(w)|=(x);\
	rhine_mii_write((p),(i),(w));\
} while (0)

#define MII_REG_BITS_OFF(x,i,p) do {\
	U16	w;\
	rhine_mii_read((p),(i),&(w));\
	(w)&=(~(x));\
	rhine_mii_write((p),(i),(w));\
} while (0)

#define MII_REG_BITS_IS_ON(x,i,p) ({\
	U16	w;\
	rhine_mii_read((p),(i),&(w));\
	((BOOL) ((w) & (x)));})

static inline void rhine_set_duplex(PRHINE_INFO pInfo, BOOL bFlag) {
	PMAC_REGS	pMacRegs=pInfo->pMacRegs;
	
	if (bFlag) 
		BYTE_REG_BITS_ON(CR1_FDX, &pMacRegs->byCR1);
	else 
		BYTE_REG_BITS_OFF(CR1_FDX, &pMacRegs->byCR1);	
			
	if (pInfo->byRevId>=REV_ID_VT6102_A)
		writeb(WOLCFG_SFDX, &pMacRegs->byWOLCGSet);
	else	
		writeb(WOLCFG_SFDX, &pMacRegs->byWOLCGClr);
		
}

static inline void
rhine_set_tx_thresh(PRHINE_INFO pInfo, int tx_thresh) {
	PMAC_REGS pMacRegs=pInfo->pMacRegs;
	BYTE_REG_BITS_SET(tx_thresh <<3, 
		(BCR1_CTSF|BCR1_CTFT1|BCR1_CTFT0), &pMacRegs->byBCR1);
			
	BYTE_REG_BITS_SET(tx_thresh <<5, 
		(TCR_RTSF|TCR_RTFT1|TCR_RTFT0), &pMacRegs->byTCR);
}

static inline void
rhine_set_rx_thresh(PRHINE_INFO pInfo, int rx_thresh) {
	PMAC_REGS pMacRegs=pInfo->pMacRegs;
	BYTE_REG_BITS_SET(rx_thresh <<3, 
		(BCR0_CRFT2|BCR0_CRFT1|BCR0_CRFT0), &pMacRegs->byBCR0);
		
	BYTE_REG_BITS_SET(rx_thresh <<5, 
		(RCR_RRFT2|RCR_RRFT1|RCR_RRFT0), &pMacRegs->byRCR);
}

static inline void
rhine_set_DMA_length(PRHINE_INFO pInfo, int DMA_length) {
	PMAC_REGS pMacRegs=pInfo->pMacRegs;
	BYTE_REG_BITS_SET(DMA_length,
		(BCR0_DMAL2|BCR0_DMAL1|BCR0_DMAL0),&pMacRegs->byBCR0);
}

static inline void
rhine_ClearISR(PMAC_REGS	pMacRegs) {
	writew(0xFFFF,&pMacRegs->byISR0);
	writeb(0xDF,&pMacRegs->byMISR);	
}

#define WAIT_MAC_TX_OFF(pMacRegs)	do {udelay(5);} while (BYTE_REG_BITS_IS_ON(CR0_TXON,&(pMacRegs)->byCR0))

inline static U32 rhine_ReadISR(PMAC_REGS pMacRegs, U8 byRevId) {
	U32	status=0;
	status=readw(&pMacRegs->byISR0);
	if (byRevId>REV_ID_VT6102_A) 
		status|=(readb(&pMacRegs->byMISR) <<16);
	return status;
}

inline static void rhine_WriteISR(int status,PMAC_REGS pMacRegs, U8 byRevId)	{
	writew((status & 0xFFFF),&pMacRegs->byISR0);
	if (byRevId>REV_ID_VT6102_A) 
		writeb((status>>16) & 0xFF,&pMacRegs->byMISR);
}

U32 rhine_check_media_mode(PRHINE_INFO pInfo);
void rhine_get_cam_mask(PRHINE_INFO pInfo, PU32 pMask, RHINE_CAM_TYPE cam_type);
void rhine_set_cam_mask(PRHINE_INFO pInfo, U32 Mask, RHINE_CAM_TYPE cam_type);
void rhine_set_cam(PRHINE_INFO pInfo, int idx, PU8 addr, RHINE_CAM_TYPE cam_type);
void rhine_get_cam(PRHINE_INFO pInfo, int idx, PU8 addr, RHINE_CAM_TYPE cam_type);
#endif