rhine.h

联想网卡驱动 linux环境下编写 初写驱动的同志参考以下

#define BCR0_DMAL0          0x01        //

//

// Bits in the BCR1 register
//
#define BCR1_MED1           0x80        // for VT6102
#define BCR1_MED0           0x40        // for VT6102
#define BCR1_VIDFR			0x80		// for VT6105
#define BCR1_TXQNOBK		0x40		// for VT6105
#define BCR1_CTSF           0x20        //
#define BCR1_CTFT1          0x10        //
#define BCR1_CTFT0          0x08        //
#define BCR1_POT2           0x04        //
#define BCR1_POT1           0x02        //
#define BCR1_POT0           0x01        //

//
// Bits in the CFGA register
//
#define CFGA_EELOAD         0x80        // enable eeprom embeded and direct programming
#define CFGA_LED0S0         0x01        //
//
// Bits in the CFGB register
//
#define CFGB_QPKTDIS        0x80        //
#define CFGB_MRLDIS         0x20        //

//
// Bits in the CFGC register
//
#define CFGC_BOOT_RPL		((BYTE) 0x80) //Boot method selection for VT3106
#define CFGC_MEDEN          0x80        //
#define CFGC_BROPT          0x40        //
#define CFGC_DLYEN          0x20        //
#define CFGC_DTSEL          0x10        //
#define CFGC_BTSEL          0x08        //
#define CFGC_BPS2           0x04        // bootrom select[2]
#define CFGC_BPS1           0x02        // bootrom select[1]
#define CFGC_BPS0           0x01        // bootrom select[0]

typedef enum {
	RHINE_VLAN_ID_CAM,
	RHINE_MULTICAST_CAM
} RHINE_CAM_TYPE, *PRHINE_CAM_TYPE;
//
// Bits in the CAMCR register
//
#define CAMC_CAMRD          0x08    
#define CAMC_CAMWR          0x04    
#define CAMC_VCAMSL         0x02    
#define CAMC_CAMEN          0x01    

//
// Bits in the CFGD register
//
#define CFGD_GPIOEN         0x80        //
#define CFGD_DIAG           0x40        //
#define CFGD_MAGIC          0x10        //
#define CFGD_CRADOM         0x08        //
#define CFGD_CAP            0x04        //
#define CFGD_MBA            0x02        //
#define CFGD_BAKOPT         0x01        //

// for VT6102 

// Bits in STICKHW
#define STICKHW_LEGWOLEN        0x0080  // status for software reference
#define STICKHW_LEGACY_WOLSR    0x0008
#define STICKHW_LEGACY_WOLEN    0x0004
#define STICKHW_DS1_SHADOW      0x0002  // R/W by software/cfg cycle
#define STICKHW_DS0_SHADOW      0x0001  // suspend well DS write port

// Bits in MISC.CR0
#define MISC_CR0_TM0US          0x20
#define MISC_CR0_FDXTFEN        0x10    // Full-duplex flow control TX enable
#define MISC_CR0_FDXRFEN        0x08    // Full-duplex flow control RX enable
#define MISC_CR0_HDXFEN         0x04    // Half-duplex flow control enable
#define MISC_CR0_TIMER0_SUSPEND 0x02
#define MISC_CR0_TIMER0_EN      0x01

// Bits in MISC.CR1
#define MISC_CR1_FORSRST        0x40
#define MISC_CR1_VAUXJMP        0x20
#define MISC_CR1_PHYINT         0x02
#define MISC_CR1_TIMER1_EN      0x01

// Bits in BPCMD
#define BPCMD_BPDNE             0x80
#define BPCMD_EBPWR             0x02
#define BPCMD_EBPRD             0x01

// Bits in MISR
#define MISR_PWEINT             0x80    // power event report in test mode
#define MISR_UDPINT_CLR         0x40    // userdefined, host driven interrupt.clear
#define MISR_UDPINT_SET         0x20    // userdefined, host driven interrupt.Set
#define MISR_SSRCI              0x10    // suspend well mii polling status change interrupt
#define MISR_TDWBRAI            0x08    // TD WB queue race
#define MISR_PHYINT             0x04    // PHY state change interrupt, active by
					// PHYINTEN (misc.cr[9]) in normal mode
#define MISR_TM1_INT            0x02
#define MISR_TM0_INT            0x01

// Bits in WOLCR
#define WOLCR_LNKOFF_EN         0x80    // link off detected enable
#define WOLCR_LNKON_EN          0x40    // link on detected enable
#define WOLCR_MAGPKT_EN         0x20    // magic packet filter enable
#define WOLCR_UNICAST_EN        0x10    // unicast filter enable
#define WOLCR_MSWOLEN3          0x08    // enable pattern match filtering
#define WOLCR_MSWOLEN2          0x04
#define WOLCR_MSWOLEN1          0x02
#define WOLCR_MSWOLEN0          0x01


// Bits in PWCFG
#define PWCFG_SMIITIME          0x80    // internal MII I/F timing
#define PWCFG_PCISTICK          0x40    // PCI sticky R/W enable
#define PWCFG_WOLTYPE           0x20    // pulse(1) or button (0)
#define PWCFG_LEGCY_WOL                 0x10    
#define PWCFG_PMCSR_PME_SR      0x08  
#define PWCFG_PMCSR_PME_EN      0x04    // control by PCISTICK
#define PWCFG_LEGACY_WOLSR      0x02    // Legacy WOL_SR shadow
#define PWCFG_LEGACY_WOLEN      0x01    // Legacy WOL_EN shadow

// Bits in TestReg
#define TSTREG_SGENWATCH        0x08  
#define TSTREG_SMCSNOOP         0x04
#define TSTREG_SMACTEST         0x02
#define TSTREG_SNORMAL          0x01

// Bits in WOLCFG
#define WOLCFG_PME_OVR          0x80    // for legacy use, force PMEEN always
#define WOLCFG_SFDX             0x40    // full duplex while in WOL mode
#define WOLCFG_SAM              0x20    // accept multicast case reset, default=0
#define WOLCFG_SAB              0x10    // accept broadcast case reset, default=0
#define WOLCFG_SMIIACC          0x08    // ??
#define WOLCFG_SMIIOPT          0x04    // MIIOPT to extend clock in suspendwell
#define WOLCFG_SSRCEN           0x02    // suspend well mii status change enable
#define WOLCFG_PHYINTEN         0x01    // 0:PHYINT trigger enable, 1:use internal MII
					// to report status change

// Ethernet address filter type
#define PKT_TYPE_NONE               0x0000  // turn off receiver
#define PKT_TYPE_DIRECTED           0x0001  // obselete, directed address is always accepted
#define PKT_TYPE_MULTICAST          0x0002
#define PKT_TYPE_ALL_MULTICAST      0x0004
#define PKT_TYPE_BROADCAST          0x0008
#define PKT_TYPE_PROMISCUOUS        0x0020
#define PKT_TYPE_LONG               0x2000  // NOTE.... the definition of LONG is >2048 bytes in our chip
#define PKT_TYPE_RUNT               0x4000
#define PKT_TYPE_ERROR              0x8000  // accept error packets, e.g. CRC error


// Loopback mode
#define MAC_LB_NONE         0x00        //
#define MAC_LB_INTERNAL     0x01        //
#define MAC_LB_PHY          0x02        // MII or Internal-10BaseT loopback


// Forced media type
#define FORCED_MEDIA_NONE       0x00    //
#define FORCED_MEDIA_AUTO       0x01    //
#define FORCED_MEDIA_100M_HALF  0x02    // hub card
#define FORCED_MEDIA_100M_FULL  0x03    // fiber channel
#define FORCED_MEDIA_10M_HALF   0x04    //
#define FORCED_MEDIA_10M_FULL   0x05    //

//
// Registers in the MII (offset unit is WORD)
//
#define MII_REG_BMCR        0x00        // physical address
#define MII_REG_BMSR        0x01        // 
#define MII_REG_PHYID1      0x02        // OUI
#define MII_REG_PHYID2      0x03        // OUI + Module ID + REV ID
#define MII_REG_ANAR        0x04        // 
#define MII_REG_ANLPAR      0x05        //
#define MII_REG_MODCFG		0x10
// NS, MYSON only
#define MII_REG_PCR         0x17        // 
// ESI only
#define MII_REG_PCSR        0x17        // 

//
// Bits in the BMCR register
//
#define BMCR_RESET          0x8000      // 
#define BMCR_LBK            0x4000      // 
#define BMCR_SPEED          0x2000      // 
#define BMCR_AUTO           0x1000      // 
#define BMCR_PD             0x0800      // 
#define BMCR_ISO            0x0400      // 
#define BMCR_REAUTO         0x0200      // 
#define BMCR_FDX            0x0100      // 

//
// Bits in the BMSR register
//
#define BMSR_AUTOCM         0x0020      // 
#define BMSR_LNK            0x0004      // 

//
// Bits in the ANAR register
//
#define ANAR_ASMDIR         0x0800      // Asymmetric PAUSE support
#define ANAR_PAUSE          0x0400      // Symmetric PAUSE Support
#define ANAR_T4             0x0200      // 
#define ANAR_TXFD           0x0100      // 
#define ANAR_TX             0x0080      // 
#define ANAR_10FD           0x0040      // 
#define ANAR_10             0x0020      // 

//
// Bits in the ANLPAR register
//
#define ANLPAR_ASMDIR       0x0800      // Asymmetric PAUSE support
#define ANLPAR_PAUSE        0x0400      // Symmetric PAUSE Support
#define ANLPAR_T4           0x0200      // 
#define ANLPAR_TXFD         0x0100      // 
#define ANLPAR_TX           0x0080      // 
#define ANLPAR_10FD         0x0040      // 
#define ANLPAR_10           0x0020      // 

//
// Bits in the RSR0 register
//
#define RSR0_BUFF           0x80        //
#define RSR0_FRAG			0x40
#define RSR0_SERR           0x40        //
#define RSR0_RUNT           0x20        //
#define RSR0_LONG           0x10        //
#define RSR0_FOV            0x08        //
#define RSR0_FAE            0x04        //
#define RSR0_CRC            0x02        //
#define RSR0_RERR           0x01        //

//
// Bits in the RSR1 register
//
#define RSR1_RXOK           0x80        // rx OK
#define RSR1_VIDHIT         0x40        // VID Hit
#define RSR1_MAR            0x20        // MAC accept multicast address packet
#define RSR1_BAR            0x10        // MAC accept broadcast address packet
#define RSR1_PHY            0x08        // MAC accept physical address packet
#define RSR1_CHN            0x04        // chain buffer, always = 1
#define RSR1_STP            0x02        // start of packet
#define RSR1_EDP            0x01        // end of packet

#define PQSTS_RXLERR		0x80
#define PQSTS_SNPTAG		0x40
#define PQSTS_IPOK          0x20        //IP Checkusm validatiaon ok
#define PQSTS_TUOK          0x10        //TCP/UDP Checkusm validatiaon ok
#define PQSTS_IPKT          0x08        //Received an IP packet
#define PQSTS_TCPKT         0x04        //Received a TCP packet
#define PQSTS_UDPKT         0x02        //Received a UDP packet
#define PQSTS_TAG           0x01        //Received a tagged packet

//
// Bits in the TSR0 register
//
#define TSR0_CDH            0x80        // AQE test fail (CD heartbeat)
#define TSR0_COLS           0x10        // experience collision in this transmit event
#define TSR0_NCR3           0x08        // collision retry counter[3]
#define TSR0_NCR2           0x04        // collision retry counter[2]
#define TSR0_NCR1           0x02        // collision retry counter[1]
#define TSR0_NCR0           0x01        // collision retry counter[0]

//
// Bits in the TSR1 register
//
#define TSR1_TERR           0x80        //
#define TSR1_JAB            0x40        // jabber condition occured
#define TSR1_SERR           0x20        //
#define TSR1_TBUFF          0x10        //
#define TSR1_UDF            0x08        //
#define TSR1_CRS            0x04        //
#define TSR1_OWC            0x02        // late collision
#define TSR1_ABT            0x01        //

//
// Bits in the TCR register
//
#define TCR_IC              0x80        // assert interrupt immediately 
                                        // while descriptor has been send complete
#define TCR_EDP             0x40        // end of packet
#define TCR_STP             0x20        // start of packet
#define TCR_TCPCK           0x10        // request TCP checksum calculation.
#define TCR_UDPCK           0x08        // request UDP checksum calculation.
#define TCR_IPCK            0x04        // request TCP checksum calculation.
#define TCR_TAG				0x02		// Do insert tag
#define TCR_CRC             0x01        // disable CRC generation

//
// Bits in the FlowCR1 register
//
#define FLOWCR1_XHITH1		0x80
#define FLOWCR1_XHITH0		0x40
#define FLOWCR1_XLTH1		0x20
#define FLOWCR1_XLTH0		0x10
#define FLOWCR1_XONEN		0x08
#define FLOWCR1_FDXTFCEN	0x04
#define FLOWCR1_FDXRFCEN	0x02
#define FLOWCR1_HDXFCEN		0x01

//
// revision id
//
#define REV_ID_VT86C100A_E  0x04
#define REV_ID_VT6102_A     0x40
#define REV_ID_VT6102_C     0x42
#define REV_ID_VT6105_A0	0x80
#define REV_ID_VT6105_B0	0x83
#define REV_ID_VT6105M_A0	0x90
#define REV_ID_VT6105M_B1	0x94

typedef struct __chip_info_tbl{
	CHIP_TYPE	chip_id;
	char*		name;	
	int			io_size;
	int			nTxQueue;
	U32			flags;
} CHIP_INFO, *PCHIP_INFO;

typedef struct __rdesc0 {
	BYTE	byRSR0;
	BYTE	byRSR1;
	U16		f15Length:15;
	U16		f1Owner:1;	
} __attribute__ ((__packed__))
RDESC0, *PRDESC0;

typedef struct __rdesc1 {
	volatile	U16		f15BufLen:15;
	volatile	U16		f1Reserved:1;
	volatile	U8		byPQSTS;
	volatile	U8		byIPKT;	
} __attribute__ ((__packed__))
RDESC1, *PRDESC1;

typedef struct {
	struct sk_buff*		skb;
	dma_addr_t			skb_dma;
	dma_addr_t			curr_desc;
} RHINE_RD_INFO,	*PRHINE_RD_INFO;

static inline PRHINE_RD_INFO alloc_rd_info(void) {
	PRHINE_RD_INFO	ptr;
	if ((ptr=kmalloc(sizeof(RHINE_RD_INFO),GFP_ATOMIC))==NULL)
		return NULL;
	else {
		memset(ptr,0,sizeof(RHINE_RD_INFO));
		return ptr;
	}
}

typedef enum {
	OWNED_BY_HOST=0,
	OWNED_BY_NIC=1
} RHINE_OWNER_TYPE, *PRHINE_OWNER_TYPE;

typedef struct __rx_desc {
	volatile RDESC0				rdesc0;
	volatile RDESC1				rdesc1;
	volatile U32				buff_addr;
	volatile U32				next_desc;
	struct __rx_desc			*next;		//4 bytes
	volatile PRHINE_RD_INFO		pInfo;		//4 bytes
	volatile U32				Reserved[2];//8 bytes
} __attribute__ ((__packed__))
RX_DESC, *PRX_DESC;

typedef struct __tx_desc0 {
	volatile	BYTE	byTSR0;
	volatile	BYTE	byTSR1;
	volatile	U16		f12VID:12;
	volatile	U16		f3Priority:3;
	volatile	U16		f1Owner:1;
} __attribute__ ((__packed__))
TDESC0, *PTDESC0;

typedef struct __tx_desc1 {
	volatile	U16			f15BufLen:15;
	volatile	U16			f1Chain:1;
	volatile	BYTE		byTCR;
	volatile	BYTE		byReserved;
} __attribute ((__packed__))
TDESC1, *PTDESC1;

typedef struct {