rhine.h

联想网卡驱动 linux环境下编写 初写驱动的同志参考以下

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 Copyright (c) 2001 - 2002, VIA Technologies, Inc.

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#ifndef RHINE_H
#define RHINE_H

#ifdef MODULE
#ifdef MODVERSIONS
#include <linux/modversions.h>
#endif /* MODVERSIONS */
#include <linux/module.h>
#endif /* MODULE */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/version.h>
#include <linux/string.h>
#include <linux/wait.h>
#include <asm/io.h>

#include <linux/if.h>
#include <linux/config.h>
#include <asm/uaccess.h>
#include <linux/proc_fs.h>

#include "kcompat.h"
#include "rhine_cfg.h"

#ifdef CONFIG_PROC_FS
#include "rhine_proc.h"
#endif


#ifdef RHINE_DEBUG
#define ASSERT(x) { \
	if (!(x)) { \
		printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\
		__FUNCTION__, __LINE__);\
		*(int*) 0=0;\
	}\
}
#else
#define ASSERT(x)	
#endif

typedef enum __rhine_msg_level {
	MSG_LEVEL_ERR=0,            //Errors that will cause abnormal operation.
	MSG_LEVEL_NOTICE=1,			//Some errors need users to be notified.
	MSG_LEVEL_INFO=2,           //Normal message.
	MSG_LEVEL_VERBOSE=3,        //Will report all trival errors.
	MSG_LEVEL_DEBUG=4           //Only for debug purpose.
} RHINE_MSG_LEVEL, *PRHINE_MSG_LEVEL;

#define RHINE_PRT(l, p, args...) {if (l<=msglevel) printk( p ,##args);}

#ifdef VMNS
#include "rhine_vmns.h"
#endif
#define W_MAX_TIMEOUT		0x3fff
//
// Registers in the MAC  
//
#define MAC_REG_PAR         0x00        // physical address
#define MAC_REG_RCR         0x06        // 
#define MAC_REG_TCR         0x07        // 
#define MAC_REG_CR0         0x08        // 
#define MAC_REG_CR1         0x09        //
#define MAC_REG_TQWK        0x0A
#define MAC_REG_ISR         0x0C        //
#define MAC_REG_IMR         0x0E        // 
#define MAC_REG_MAR         0x10        //
#define MAC_REG_MCAM		0x10        //
#define MAC_REG_VCAM		0x16		//
#define MAC_REG_CUR_RD_ADDR 0x18        // 
#define MAC_REG_CUR_TD_ADDR 0x1C        // 
#define MAC_REG_RX_DMA_PTR  0x60        // 
#define MAC_REG_MPHY        0x6C        // 
#define MAC_REG_MIISR       0x6D        // 
#define MAC_REG_BCR0        0x6E        // 
#define MAC_REG_BCR1        0x6F        // 
#define MAC_REG_MIICR       0x70        // 
#define MAC_REG_MIIAD       0x71        // 
#define MAC_REG_MIIDATA     0x72        // 
#define MAC_REG_EECSR       0x74        // 
#define MAC_REG_TEST        0x75        // 
#define MAC_REG_CFGA        0x78        // 
#define MAC_REG_CFGB        0x79        // 
#define MAC_REG_CFGC        0x7A        // 
#define MAC_REG_CFGD        0x7B        // 
#define MAC_REG_CNTR_MPA    0x7C        // 
#define MAC_REG_CNTR_CRC    0x7E        // 

// Registers for VT6102
#define MAC_REG_GFTEST      0x54    //
#define MAC_REG_RFTCMD      0x55    //
#define MAC_REG_TFTCMD      0x56    //
#define MAC_REG_GFSTATUS    0x57    //
#define MAC_REG_BNRY        0x58    // 
#define MAC_REG_CURR        0x5A    //
#define MAC_REG_FIFO_DATA   0x5C    //
#define MAC_REG_CUR_RXDMA   0x60    //
#define MAC_REG_CUR_TXDMA   0x64    //

#define MAC_REG_MISC_CR0    0x80    //
#define MAC_REG_MISC_CR1    0x81    //
#define MAC_REG_PMCPORT     0x82    //
#define MAC_REG_STICKHW     0x83    //
#define MAC_REG_MISR        0x84    //
#define MAC_REG_MIMR        0x86    //
#define MAC_REG_CAMMSK      0x88    //
#define MAC_REG_BPMA        0x8C    //
#define MAC_REG_BPMD        0x8F    //
#define MAC_REG_BPCMD       0x90    //
#define MAC_REG_BPIN_DATA   0x91    //
#define MAC_REG_CAMC        0x92    //
#define MAC_REG_CAMADD   	0x93    //
#define MAC_REG_EECHKSUM    0x93    //
#define MAC_REG_SUS_MII_AD  0x94    //
#define MAC_REG_MIBCR       0x94
#define MAC_REG_MIBDATA		0x96	//
#define MAC_REG_SUS_PHY_ID  0x96    //
#define MAC_REG_MIBPORT     0x96    //
#define MAC_REG_MIBDAT      0x97    //
#define MAC_REG_PAUSE_TIMER 0x98    //
#define MAC_REG_FLOWCR0		0x98
#define MAC_REG_SOFT_TIMER0 0x9C    //
#define MAC_REG_SOFT_TIMER1 0x9E    //
#define MAC_REG_WOLCR_SET   0xA0    //
#define MAC_REG_PWCFG_SET   0xA1    //
#define MAC_REG_TSTREG_SET  0xA2    //
#define MAC_REG_WOLCG_SET   0xA3    //
#define MAC_REG_WOLCR_CLR   0xA4    //
#define MAC_REG_PWCFG_CLR   0xA5    //
#define MAC_REG_TSTREG_CLR  0xA6    //
#define MAC_REG_WOLCG_CLR   0xA7    //
#define MAC_REG_PWRCSR_SET  0xA8    //
#define MAC_REG_PWRCSR_CLR  0xAC    //
#define MAC_REG_PATRN_CRC0  0xB0    //
#define MAC_REG_PATRN_CRC1  0xB4    //
#define MAC_REG_PATRN_CRC2  0xB8    //
#define MAC_REG_PATRN_CRC3  0xBC    //
#define MAC_REG_BYTEMSK0_0  0xC0    //
#define MAC_REG_BYTEMSK0_1  0xC4    //
#define MAC_REG_BYTEMSK0_2  0xC8    //
#define MAC_REG_BYTEMSK0_3  0xCC    //
#define MAC_REG_BYTEMSK1_0  0xD0    //
#define MAC_REG_BYTEMSK1_1  0xD4    //
#define MAC_REG_BYTEMSK1_2  0xD8    //
#define MAC_REG_BYTEMSK1_3  0xDC    //
#define MAC_REG_BYTEMSK2_0  0xE0    //
#define MAC_REG_BYTEMSK2_1  0xE4    //
#define MAC_REG_BYTEMSK2_2  0xE8    //
#define MAC_REG_BYTEMSK2_3  0xEC    //
#define MAC_REG_BYTEMSK3_0  0xF0    //
#define MAC_REG_BYTEMSK3_1  0xF4    //
#define MAC_REG_BYTEMSK3_2  0xF8    //
#define MAC_REG_BYTEMSK3_3  0xFC    //

#define BYTE_REG_BITS_ON(x,p)	do { writeb(readb((p))|(x),(p));} while (0)

#define WORD_REG_BITS_ON(x,p)	do { writew(readw((p))|(x),(p));} while (0)
#define DWORD_REG_BITS_ON(x,p)	do { writel(readl((p))|(x),(p));} while (0)

#define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x))
#define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x))
#define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x))

#define BYTE_REG_BITS_OFF(x,p)	do { writeb(readb((p)) & (~(x)),(p));} while (0)
#define WORD_REG_BITS_OFF(x,p)	do { writew(readw((p)) & (~(x)),(p));} while (0)
#define DWORD_REG_BITS_OFF(x,p)	do { writel(readl((p)) & (~(x)),(p));} while (0)

#define BYTE_REG_BITS_SET(x,m,p)	do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
#define WORD_REG_BITS_SET(x,m,p)	do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
#define DWORD_REG_BITS_SET(x,m,p)	do { writel( (readl((p)) & (~(m)))|(x),(p));}  while (0)


//
// Bits in the RCR register
//
#define RCR_RRFT2           0x80        //
#define RCR_RRFT1           0x40        //
#define RCR_RRFT0           0x20        //
#define RCR_PROM            0x10        //
#define RCR_AB              0x08        //
#define RCR_AM              0x04        //
#define RCR_AR              0x02        //
#define RCR_SEP             0x01        //

//
// Bits in the TCR register
//
#define TCR_RTSF            0x80        //
#define TCR_RTFT1           0x40        //
#define TCR_RTFT0           0x20        //
#define TCR_RTGOPT			0x10		//
#define TCR_OFSET           0x08        //
#define TCR_LB1             0x04        // loopback[1]
#define TCR_LB0             0x02        // loopback[0]
#define	TCR_PQEN			0x01

//
// Bits in the CR0 register
//
#define CR0_RDMD            0x40        // rx descriptor polling demand
#define CR0_TDMD            0x20        // tx descriptor polling demand
#define CR0_TXON            0x10        // 
#define CR0_RXON            0x08        //
#define CR0_STOP            0x04        // stop MAC, default = 1
#define CR0_STRT            0x02        // start MAC
#define CR0_INIT            0x01        // start init process

#define CR0_SFRST           0x8000      // software reset
#define CR0_RDMD1           0x4000      //
#define CR0_TDMD1           0x2000      //
#define CR0_KEYPAG          0x1000      //
#define CR0_DPOLL           0x0800      // disable rx/tx auto polling
#define CR0_FDX             0x0400      // full duplex mode
#define CR0_ETEN            0x0200      // early tx mode
#define CR0_EREN            0x0100      // early rx mode
//
// Bits in the CR1 register
//
#define CR1_SFRST           0x80        // software reset
#define CR1_RDMD1           0x40        //
#define CR1_TDMD1           0x20        //
#define CR1_REAUTO			0x10		// for VT6105
#define CR1_KEYPAG          0x10        //
#define CR1_DPOLL           0x08        // disable rx/tx auto polling
#define CR1_FDX             0x04        // full duplex mode
#define CR1_DISAU			0x02		// for VT6105
#define CR1_ETEN            0x02        // early tx mode
#define CR1_EREN            0x01        // early rx mode

//
// Bits in the IMR register
//
#define IMR_KEYM            0x8000      //
#define IMR_SRCM            0x4000      //
#define IMR_ABTM            0x2000      //
#define IMR_NORBFM          0x1000      //
#define IMR_PKTRAM          0x0800      //
#define IMR_OVFM            0x0400      //
#define IMR_ETM             0x0200      //
#define IMR_ERM             0x0100      //
#define IMR_CNTM            0x0080      //
#define IMR_BEM             0x0040      //
#define IMR_RUM             0x0020      //
#define IMR_TUM             0x0010      //
#define IMR_TXEM            0x0008      //
#define IMR_RXEM            0x0004      //
#define IMR_PTXM            0x0002      //
#define IMR_PRXM            0x0001      //

#define IMR_TDWBRAI			0x00080000UL //
//
// Bits in the ISR (MISR) register
//
#define ISR_GENI            0x00008000UL    //  for 6102
#define ISR_SRCI            0x00004000UL    //
#define ISR_ABTI            0x00002000UL    //
#define ISR_NORBF           0x00001000UL    //
#define ISR_PKTRA           0x00000800UL    //
#define ISR_OVFI            0x00000400UL    //
#define ISR_UDFI            0x00000200UL    //  for 6102
#define ISR_ERI             0x00000100UL    //
#define ISR_CNT             0x00000080UL    //
#define ISR_BE              0x00000040UL    //
#define ISR_RU              0x00000020UL    //
#define ISR_TU              0x00000010UL    //
#define ISR_TXE             0x00000008UL    //
#define ISR_RXE             0x00000004UL    //
#define ISR_PTX             0x00000002UL    //
#define ISR_PRX             0x00000001UL    //
// Bits in MISR
#define ISR_PWEINT          0x00800000UL    // power event report in test mode
#define ISR_UDPINT_CLR      0x00400000UL    // userdefined, host driven interrupt.clear
#define ISR_UDPINT_SET      0x00200000UL    // userdefined, host driven interrupt.Set
#define ISR_SSRCI           0x00100000UL    // suspend well mii polling status change interrupt
#define ISR_TDWBRAI         0x00080000UL    // TD WB queue race
#define ISR_PHYINT          0x00040000UL    // PHY state change interrupt, active by
					    // PHYINTEN (misc.cr[9]) in normal mode
#define ISR_TM1_INT         0x00020000UL    //
#define ISR_TM0_INT         0x00010000UL    //


//
// Bits in the MIISR register
//
#define MIISR_N_FDX			0x04
#define MIISR_LNKFL         0x02        //
#define MIISR_SPEED         0x01        //

//
// Bits in the MIICR register
//
#define MIICR_MAUTO         0x80        //
#define MIICR_RCMD          0x40        //
#define MIICR_WCMD          0x20        //
#define MIICR_MDPM          0x10        //
#define MIICR_MOUT          0x08        //
#define MIICR_MDO           0x04        //
#define MIICR_MDI           0x02        //
#define MIICR_MDC           0x01        //

//
// Bits in the MIIAD register
//
#define MIIAD_MIDLE         0x80        //
#define MIIAD_MSRCEN        0x40        //
#define MIIAD_MDONE         0x20        //
//
// Bits in the MIBCR register
//
#define MIBCR_MIBEN			0x10
#define MIBCR_MIBHALF		0x20
#define MIBCR_MIBINC		0x40
#define MIBCR_MIBRTN		0x80
//
// Bits in the EECSR register
//
#define EECSR_EEPR          0x80        // eeprom programed status, 73h means programed
#define EECSR_EMBP          0x40        // eeprom embeded programming
#define EECSR_AUTOLD        0x20        // eeprom content reload
#define EECSR_DPM           0x10        // eeprom direct programming
#define EECSR_CS            0x08        // eeprom CS pin
#define EECSR_SK            0x04        // eeprom SK pin
#define EECSR_DI            0x02        // eeprom DI pin
#define EECSR_DO            0x01        // eeprom DO pin

//
// Bits in the BCR0 register
//
#define BCR0_BOOT_MASK		((BYTE) 0xC0)
#define BCR0_BOOT_INT19		((BYTE) 0x00)
#define BCR0_BOOT_INT18     ((BYTE) 0x40)
#define BCR0_BOOT_LOCAL		((BYTE) 0x80)
#define BCR0_BOOT_BEV		((BYTE) 0xC0)

#define BCR0_MED2           0x80        //
#define BCR0_LED100M        0x40        //
#define BCR0_CRFT2          0x20        //
#define BCR0_CRFT1          0x10        //
#define BCR0_CRFT0          0x08        //
#define BCR0_DMAL2          0x04        //
#define BCR0_DMAL1          0x02        //