forward.v

openaccess与verilog互相转化时所用的源代码

// Forward Reference Test


module top();
    wire        a, b, c;
    wire [1:0]  d, e;
    
    mid named(.v(a), .z(e), .w(b), .x(c), .y(d));
    mid order(a, b, c, d, e);
endmodule



module mid(inout v, w, x, 
           inout [1:0] y,
           inout [1:2] z);
    wire        a, b, c;
    wire [3:0]  d, e;
    
    bottom order[1:0](a, b, c, d, e);
    bottom named[1:0](.v(a), .z(e), .w(b), .x(c), .y(d));
endmodule



module bottom(inout v, w, x, 
              inout [1:0] y, z);
endmodule