concat.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 60 行

// Test the parser's ability to handle concatenations.


module simple(inout [1:0] a);
    wire b, c;
    assign a = {b,c};
endmodule


module multi(inout [31:0] a);
    wire [3:0] b;
    assign a = {8{b}};
endmodule


module numerical(inout [63:0] a);
    assign a = {32'h80000000, 32'h00000001};
endmodule


module multiNumerical(inout [63:0] a);
    assign a = {16{4'b0001}};
endmodule


module nested(inout [63:0] a);
    wire [3:0] b;
    assign a = {2{{4{4'b001}}, {4{b}}}};
endmodule


module complex();
    wire a;
    wire [3:0] b;
    wire [1:0] c;
    
    wire [7:0] x;
    assign x = {a, a, b[3:0], c[1], c[0]};
endmodule


module combination(input [1:0] in, output out);
    wire [1:0] bus;
    
    simple I1(.a({in[0], bus[0]}));
    simple I2(.a({in[1], out}));
endmodule
    

module top();
    simple          I1();
    multi           I2();
    numerical       I3();
    multiNumerical  I4();
    nested          I5();
    complex         I6();
endmodule