inouttest.v

openaccess与verilog互相转化时所用的源代码

module top(inout v, w, x, 
           inout [1:0] y, z);
    wire        a, b, c;
    wire [1:0]  d, e;
    bottom order(a, b, c, d, e);
    bottom named(.v(a), .z(e), .w(b), .x(c), .y(d));
endmodule



module bottom(inout v, w, x, 
              inout [1:0] y, z);
endmodule