ansiports.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 21 行

module XOR(output out, input a,b);
	always //@(a,b,out) 
	   out = a^b;
endmodule


module top
	(output [1:8] xout,
	 input  [1:8] xin1, xin2);

	XOR a(xout[8],xin1[8],xin2[8]),
	    b(xout[7],xin1[7],xin2[7]),
	    c(xout[6],xin1[6],xin2[6]),
	    d(xout[5],xin1[5],xin2[5]),
	    e(xout[4],xin1[4],xin2[4]),
	    f(xout[3],xin1[3],xin2[3]),
	    g(xout[2],xin1[2],xin2[2]),
	    h(xout[1],xin1[1],xin2[1]);
endmodule