gates.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 38 行

// Test gate instantiation (currently not implemented).

module top(in1, in2, in3, in4, out1, out2, out3, out4, io1, io2, en1, en2);
    input   in1, in2, in3, in4;
    output  out1, out2, out3, out4;
    inout   io1, io2;
    inout   en1, en2;

    cmos                (out1, in1, en1, en2);
    bufif0              (out1, in1, en1);
    nmos                (out1, in1, en1);
    and                 (out1, in1, in2, in3, in4);
    not                 (out1, out2, out3, out4, in1);
    tranif0             (io1, io2, en1);
    rtran               (io1, io2);
    pulldown            (out1);
    pullup              (out1);   
    
    cmos        inst1   (out1, in1, en1, en2);
    bufif0      inst2   (out1, in1, en1);
    nmos        inst3   (out1, in1, en1);
    and         inst4   (out1, in1, in2, in3, in4);
    not         inst5   (out1, out2, out3, out4, in1);
    tranif0     inst6   (io1, io2, en1);
    rtran       inst7   (io1, io2);
    pulldown    inst8   (out1);
    pullup      inst9   (out1);   

    cmos        #10 inst10  (out1, in1, en1, en2);
    bufif0      #20 inst12  (out1, in1, en1);
    nmos        #30 inst13  (out1, in1, en1);
    and         #40 inst14  (out1, in1, in2, in3, in4);
    not         #50 inst15  (out1, out2, out3, out4, in1);
    tranif0     #60 inst16  (io1, io2, en1);
  
endmodule