opnfwdref.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 10 行

// This test verifies that the reader will report the case when 
// an unresolved forward reference exists.



module unresolved();
    wire b, d;
    forward I1(.a(b), .c(d));
endmodule