termnotfoundleaf2.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 19 行

// Test the reader's ability to detect an extra terminal in the leaf cell's
// declaration.



module scalarLeaf(.in(x), .out(y), .aux(z));
    input   in;
    output  out;
    inout   aux;
    wire    a, b, c;
endmodule



module top2();
    scalarLeaf  I1(a, b, c);
endmodule