implicitwire.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 14 行

// Verify that implicit wires can be created and used.
// The cOut and x8 identifiers should be treated as implicit wires.

module NAND(output out, input in1, in2);
	always @(out,in1,in2);
endmodule

module top(output sum, input aIn, bIn, cIn);
	wire x2;

	NAND I1(x2,aIn,bIn),
	     I2(cOut,x2,x8);
endmodule