hier.v

来自「openaccess与verilog互相转化时所用的源代码」· Verilog 代码 · 共 49 行

module level1(l1_in, l1_out);
	input  [7:0] l1_in;
	output l1_out;
endmodule

module level2A(l2A_in, l2A_out);
	input  l2A_in;
	output l2A_out;

	reg [7:0] l2A_busReg;

	level1 I1(l2A_busReg, l2A_out);

endmodule


module level2B(l2B_in, l2B_out);
	input        l2B_in;
	output [1:0] l2B_out;

	reg [7:0] l2B_busReg;

	level1 I1(l2B_busReg, l2B_out[1]);

endmodule


module level3(l3_in, l3_out);
	input        l3_in;
	output [1:0] l3_out;

	level2A I1A(l3_in, l3_out[1]);
	level2B I2B(l3_in, l3_out);

endmodule


module top();

	reg        scalar1,scalar2,scalar3;
	reg [1:0]  bus1,bus2,bus3;  

	level3 I1(scalar1,bus1),
	       I2(scalar2,bus2),
	       I3(scalar3,bus3);

endmodule